count30.rpt

该程序是用一片HDPLD和若干外围电路实现的十字路口交通控制器,其中包含顶层图形文件和源文件以及仿真波形

 (39)    19    B       DFFE   +  t        0      0   0    1    5    1    8  cnt2 (:6)
 (40)    18    B       DFFE   +  t        0      0   0    1    5    1    9  cnt1 (:7)
 (31)    26    B       TFFE   +  t        0      0   0    1    5    1    5  cnt0 (:8)


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                            d:\project\count30.rpt
count30

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                             Logic cells placed in LAB 'B'
        +------------------- LC17 c
        | +----------------- LC25 |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node1
        | | +--------------- LC24 |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node2
        | | | +------------- LC23 |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node3
        | | | | +----------- LC22 |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node4
        | | | | | +--------- LC21 cnt4
        | | | | | | +------- LC20 cnt3
        | | | | | | | +----- LC19 cnt2
        | | | | | | | | +--- LC18 cnt1
        | | | | | | | | | +- LC26 cnt0
        | | | | | | | | | | 
        | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC25 -> - - - - - - - - * - | - * | <-- |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node1
LC24 -> - - - - - - - * - - | - * | <-- |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node2
LC23 -> - - - - - - * - - - | - * | <-- |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node3
LC22 -> - - - - - * - - - - | - * | <-- |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node4
LC21 -> * - - - * * * * * * | - * | <-- cnt4
LC20 -> * - - * * * * * * * | - * | <-- cnt3
LC19 -> * - * * * * * * * * | - * | <-- cnt2
LC18 -> * * * * * * * * * * | - * | <-- cnt1
LC26 -> * * * * * - - - - * | - * | <-- cnt0

Pin
43   -> - - - - - - - - - - | - - | <-- clk
4    -> - - - - - * * * * * | - * | <-- enable


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                            d:\project\count30.rpt
count30

** EQUATIONS **

clk      : INPUT;
enable   : INPUT;

-- Node name is 'c' 
-- Equation name is 'c', location is LC017, type is output.
 c       = LCELL( _EQ001 $  GND);
  _EQ001 = !cnt0 &  cnt1 &  cnt2 &  cnt3 &  cnt4;

-- Node name is ':8' = 'cnt0' 
-- Equation name is 'cnt0', location is LC026, type is buried.
cnt0     = TFFE(!_EQ002, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ002 = !cnt0 &  cnt1 &  cnt2 &  cnt3 &  cnt4
         # !cnt0 & !enable;

-- Node name is ':7' = 'cnt1' 
-- Equation name is 'cnt1', location is LC018, type is buried.
cnt1     = DFFE( _EQ003 $  _LC025, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ003 =  cnt1 &  cnt2 &  cnt3 &  cnt4 &  _LC025
         # !enable &  _LC025;

-- Node name is ':6' = 'cnt2' 
-- Equation name is 'cnt2', location is LC019, type is buried.
cnt2     = DFFE( _EQ004 $  _LC024, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ004 =  cnt1 &  cnt2 &  cnt3 &  cnt4 &  _LC024
         # !enable &  _LC024;

-- Node name is ':5' = 'cnt3' 
-- Equation name is 'cnt3', location is LC020, type is buried.
cnt3     = DFFE( _EQ005 $  _LC023, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ005 =  cnt1 &  cnt2 &  cnt3 &  cnt4 &  _LC023
         # !enable &  _LC023;

-- Node name is ':4' = 'cnt4' 
-- Equation name is 'cnt4', location is LC021, type is buried.
cnt4     = DFFE( _EQ006 $  _LC022, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ006 =  cnt1 &  cnt2 &  cnt3 &  cnt4 &  _LC022
         # !enable &  _LC022;

-- Node name is '|LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried 
_LC025   = LCELL( cnt1 $  cnt0);

-- Node name is '|LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC024', type is buried 
_LC024   = LCELL( cnt2 $  _EQ007);
  _EQ007 =  cnt0 &  cnt1;

-- Node name is '|LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC023', type is buried 
_LC023   = LCELL( cnt3 $  _EQ008);
  _EQ008 =  cnt0 &  cnt1 &  cnt2;

-- Node name is '|LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC022', type is buried 
_LC022   = LCELL( cnt4 $  _EQ009);
  _EQ009 =  cnt0 &  cnt1 &  cnt2 &  cnt3;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                     d:\project\count30.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 4,175K