accumulator.vhd

数字均衡器是通讯信道抗码间干扰的重要环节,这是一个用vhdl写的代码以及用SYNPLIFY8.0综合的RTL电路图 它包含三个模块FILTER,ERR_DECISION,ADJUST 希望对大家有用.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
--use work.equ_pak.all;

entity accumulator is
generic(n:positive:=12);
port(clk: in std_logic;
     resetn: in std_logic :='1';
     datain:  in std_logic_vector(15 downto 0);
     f_en:  in std_logic:='0';
     add_end:out std_logic;
     dataout: out std_logic_vector(17 downto 0));
end accumulator;

architecture rt1 of accumulator is
signal datainm:std_logic_vector(15 downto 0);
signal f_enm:std_logic;
begin
process(clk,resetn)
variable m1_data:std_logic_vector(17 downto 0);
variable m2_data:std_logic_vector(17 downto 0);
variable m_result:std_logic_vector(17 downto 0);
begin
if resetn='0' then
dataout<=(others=>'0');
add_end<='0';
m_result:=(others=>'0');
datainm<=(others=>'0');
f_enm<='0';
elsif clk'event and clk='1' then
datainm<=datain;
f_enm<=f_en;
if f_enm='1' then
add_end<='0';
dataout<=(others=>'0');
m1_data:="00"&datainm;
m_result:='0'&m_result(17 downto 1);
m2_data:=m_result;
m_result:=m1_data(17 downto 0)+m2_data(17 downto 0);
elsif f_enm'last_value='1' and f_enm='0' then
dataout<=m_result;
add_end<='1';
end if;
end if;
end process;
end rt1;