filter.vhd

数字均衡器是通讯信道抗码间干扰的重要环节,这是一个用vhdl写的代码以及用SYNPLIFY8.0综合的RTL电路图 它包含三个模块FILTER,ERR_DECISION,ADJUST 希望对大家有用.

library ieee;
use ieee.std_logic_1164.all;
use work.equ_pak.all;
 
entity filter is
        port(
           clk:in std_logic;
           resetn:in std_logic:='1';
           ad_end:in std_logic:='0';
           xin:in std_logic_vector(11 downto 0);
           a:in std_logic_vector(1 downto 0);
           z:out std_logic_vector(9 downto 0);
           x_ff:out data1_array(2 downto 0);
           x_main: out std_logic_vector(11 downto 0);
           x_bf: out data2_array(2 downto 0);
         filterend: out std_logic;
           
            w_addr1:in std_logic_vector(2 downto 0):=(others=>'0');
            w_addr2: in std_logic:='0';
            w_addr3:in std_logic_vector(2 downto 0):="000";
  
           data1,data2:in std_logic_vector(15 downto 0):=(others=>'0');
          data3:in std_logic_vector(15 downto 0):=(others=>'0');--8????
           ram_ch1,ram_ch2,ram_ch3:in std_logic:='0'
              );
    end filter;
 
  architecture rtl of filter is
             signal shift_en_m,load_m,shift_s12_m,shift_s3_m:std_logic;
             signal y_ff_m:data1_array(2 downto 0);
             signal y_main_m:std_logic_vector(11 downto 0);
             signal y_bf_m:data2_array(2 downto 0);
             signal addr_st_m1,addr_st_m2,addr_st_m3:std_logic;
             signal ram_addr_m1,ram_addr_m3:std_logic_vector(2 downto 0);
             signal ram_addr_m2:std_logic;
             signal coefout_m1,coefout_m2,coefout_m3:std_logic;
             signal ram_out_m1,ram_out_m2,ram_out_m3:std_logic_vector(15 downto 0);
             signal add_end_m1,add_end_m2,add_end_m3:std_logic;
             signal dataout_m1:std_logic_vector(17 downto 0);
             signal dataout_m2,dataout_m3:std_logic_vector(17 downto 0);
      begin
      u1:filter_con port map(clk,resetn,ad_end,shift_en_m,load_m,shift_s12_m,shift_s3_m);
      u2:filter_shift port map(clk,resetn,xin,a,shift_en_m,y_ff_m,y_main_m,y_bf_m);
         x_ff<=y_ff_m;
         x_main<=y_main_m;
         x_bf<=y_bf_m;
u31:s_term1 port map(clk,resetn,load_m,shift_s12_m,y_ff_m,addr_st_m1,ram_addr_m1);
u32:s_term2 port map(clk,resetn,load_m,shift_s12_m,y_main_m,addr_st_m2,ram_addr_m2);
u33:s_term3 port map(clk,resetn,load_m,shift_s3_m,y_bf_m,addr_st_m3,ram_addr_m3);
u41:filter_coef port map(clk,resetn,addr_st_m1,ram_ch1,ram_addr_m1,w_addr1,data1,ram_out_m1,coefout_m1);
u42:filter_coef1 port map(clk,resetn,addr_st_m2,ram_ch2, ram_addr_m2,w_addr2,data2,ram_out_m2,coefout_m2);
u43:filter3_coef port map(clk,resetn,addr_st_m3,ram_ch3, ram_addr_m3,w_addr3,data3,ram_out_m3,coefout_m3);
u51:accumulator port map(clk,resetn,ram_out_m1,coefout_m1,add_end_m1,dataout_m1);
u52:accumulator port map(clk,resetn,ram_out_m2,coefout_m2,add_end_m2,dataout_m2);
u53:accumulator port map(clk,resetn,ram_out_m3,coefout_m3,add_end_m3,dataout_m3);
u6:filter_add port map(clk,resetn,add_end_m1,add_end_m2,add_end_m3,dataout_m1,dataout_m2,dataout_m3,z,filterend);
end rtl;