filter_shift.vhd

数字均衡器是通讯信道抗码间干扰的重要环节,这是一个用vhdl写的代码以及用SYNPLIFY8.0综合的RTL电路图 它包含三个模块FILTER,ERR_DECISION,ADJUST 希望对大家有用.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.equ_pak.all;

ENTITY filter_shift IS
PORT(clk: in std_logic;
  resetn: in std_logic:='1';
    xin: in std_logic_vector(11 downto 0);
    a  : in std_logic_vector(1 downto 0):="00";
    s_en: in std_logic:='0';
    y_ff: out data1_array(2 downto 0);
    y_main: out std_logic_vector(11 downto 0);
    y_bf  : out data2_array(2 downto 0));
END filter_shift;

ARCHITECTURE rt1 OF filter_shift IS
SIGNAL y0,y1,y2,y3: std_logic_vector(11 downto 0);
   SIGNAL z0,z1,z2: std_logic_vector(1 downto 0);
BEGIN
shift1: FOR i in 11 downto 0 generate
         u1x:shift_4 port
map (clk, resetn, xin(i), s_en, y0(i), y1(i), y2(i), y3(i));
end generate;

y_ff(2)<=y2;
y_ff(1)<=y1;
y_ff(0)<=y0;
y_main<=y3;

shift2: FOR i in 1 downto 0 generate
u2x: shift_3 port
map(clk,resetn, a(i), s_en,  z0(i), z1(i), z2(i));
end generate;
y_bf(2)<=z2;
y_bf(1)<=z1;
y_bf(0)<=z0;
end rt1;