s_term2.vhd

数字均衡器是通讯信道抗码间干扰的重要环节,这是一个用vhdl写的代码以及用SYNPLIFY8.0综合的RTL电路图 它包含三个模块FILTER,ERR_DECISION,ADJUST 希望对大家有用.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE work.equ_pak.all;

ENTITY s_term2 IS
GENERIC(n: positive:=12);
PORT(clk: in std_logic;
resetn: in std_logic:='1';
load_n:in std_logic:='0';
shift_en: in std_logic:='0';
parallel_in : in std_logic_vector(n-1 downto 0);
serial_out: out std_logic;
addr_st: out std_logic);
END s_term2;

ARCHITECTURE rt1 OF s_term2 IS
SIGNAL load_nm, shift_enm:std_logic;
BEGIN
PROCESS(clk,resetn)
variable shift_reg:std_logic_vector(n-1 downto 0);
BEGIN
IF resetn='0' then
serial_out<='0';
shift_reg:=(others=>'0');
addr_st<='0';
load_nm<='0';
shift_enm<='0';
ELSIF clk'event and clk='1' then
load_nm<=load_n;
shift_enm<=shift_en;
IF load_nm='1' then
shift_reg:=parallel_in;
serial_out<=shift_reg(0);
addr_st<='1';
ELSIF shift_enm='1' then
shift_reg:=std_logic_vector(shr(unsigned(shift_reg),"1"));
shift_reg(n-1):='0';
serial_out<=shift_reg(0);
addr_st<='1';
ELSE
addr_st<='0';
END IF;
END IF;
END PROCESS;
END rt1;