filter_coef1.vhd

数字均衡器是通讯信道抗码间干扰的重要环节,这是一个用vhdl写的代码以及用SYNPLIFY8.0综合的RTL电路图 它包含三个模块FILTER,ERR_DECISION,ADJUST 希望对大家有用.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE work.equ_pak.all;

ENTITY filter_coef1 IS
PORT(clk: in std_logic;
resetn: in std_logic:='1';
addr_st: in std_logic:='0';
ram_ch:in std_logic:='0';
ram_addr:in std_logic:='0';
ch_addr: in std_logic:='0';
data:in std_logic_vector(15 downto 0):=(others=>'0');
ram_out:out std_logic_vector(15 downto 0);
coefout: out std_logic);
END filter_coef1;

ARCHITECTURE rt1 OF filter_coef1 IS
SIGNAL q_array:coef_array(1 downto 0);
SIGNAL data_m:std_logic_vector(15 downto 0);
SIGNAL write_s:std_logic;
SIGNAL ramout_tm:std_logic_vector(15 downto 0);
SIGNAL ram_ch_add:std_logic;
SIGNAL ch_addr_m1:std_logic;
SIGNAL ch_addr_m2:std_logic;
SIGNAL datam:std_logic_vector(15 downto 0);
SIGNAL ram_addrm:std_logic;
SIGNAL ch_addrm:std_logic;
SIGNAL addr_stm,ram_chm:std_logic;

BEGIN
writ: process(clk,resetn)
begin
if resetn='0' then
q_array(1)<=(others=>'0');
q_array(0)<=(others=>'0');
elsif clk'event and clk='1' then
if write_s='1' then
case ch_addr_m2 is
when'0' =>q_array(0)<=data_m;
when others=>q_array(1)<=data_m;
end case;
end if;
end if;
end process;
read1:process(clk,resetn)
begin
if resetn='0' then
ram_out<=(others=>'0');
coefout<='0';
ram_addrm<='0';
elsif clk'event and clk='1' then
ram_addrm<=ram_addr;
if addr_stm='1' and ram_chm='0' then
case ram_addrm is
when '0'=>ram_out<=q_array(0);
when others=>ram_out<=q_array(1);
end case;coefout<='1';
else
ram_out<=(others=>'0');
coefout<='0';
end if;
end if;
end process;

read2: process(clk, resetn)
begin
if resetn='0' then
ramout_tm<=(others=>'0');
ch_addr_m1<='0';
ch_addrm<='0';
elsif clk'event and clk='1' then
if ram_chm='1' then
ch_addrm<=ch_addr;
case ch_addrm is
when '0'=>ramout_tm<=q_array(0);
when others=>ramout_tm<=q_array(1);
end case;
ch_addr_m1<=ch_addr;
else
ramout_tm<=(others=>'0');
ch_addr_m1<='0';
end if;
end if;
end process;

addpro:process(clk,resetn)
variable m_result:std_logic_vector(16 downto 0);
begin
if resetn='0' then
write_s<='0';
data_m<=(others=>'0');
ch_addr_m2<='0';
ram_ch_add<='0';
datam<=(others=>'0');
elsif clk'event and clk='1' then
ram_ch_add<=ram_ch;
ch_addr_m2<=ch_addr_m1;
datam<=data;
if ram_ch_add='1' then
m_result:='0'&ramout_tm+datam;
data_m<=m_result(16 downto 1);
write_s<='1';
else
data_m<=(others=>'0');
write_s<='0';
end if;
end if;
end process;

process(clk,resetn)
begin
if resetn='0' then
addr_stm<='0';
ram_chm<='0';
elsif clk'event and clk='1' then
addr_stm<=addr_st;
ram_chm<=ram_ch;
end if;
end process;
end rt1;