adjust_con.vhd

数字均衡器是通讯信道抗码间干扰的重要环节,这是一个用vhdl写的代码以及用SYNPLIFY8.0综合的RTL电路图 它包含三个模块FILTER,ERR_DECISION,ADJUST 希望对大家有用.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--use work.equ_pak.all;

entity adjust_con is
              port(
                 clk:in std_logic;
             resetn:in std_logic:='1';
             adjust_en:in std_logic:='0';
             cmp1_en1:out std_logic;
             mult_en1:out std_logic;
             cmp2_en1:out std_logic;
             addrgene_en1: out std_logic;
mult_en2:out std_logic;
cmp1_en2:out std_logic;
cmp2_en2:out std_logic;
addrgene_en2: out std_logic;
mult_en3:out std_logic;
cmp1_en3:out std_logic;
cmp2_en3:out std_logic;
addrgene_en3: out std_logic
);
end adjust_con;

architecture rtl of adjust_con is
signal adjust_enm1,adjust_enm2:std_logic;
signal cmp1_en1m,cmp1_en2m,cmp1_en3m:std_logic;
signal mult_en1m,mult_en2m,mult_en3m:std_logic;
signal cmp2_en1m,cmp2_en2m,cmp2_en3m:std_logic;
begin
   process(clk,resetn)
    begin
      if resetn='0' then
          cmp1_en1<='0';
          mult_en1<='0';
          cmp2_en1<='0';
          addrgene_en1<='0';
          cmp1_en2<='0';
          mult_en2<='0';
          cmp2_en2<='0';
          addrgene_en2<='0';
          cmp1_en3<='0';
          mult_en3<='0';
          cmp2_en3<='0';
          addrgene_en3<='0';
   
   elsif clk'event and clk='1' then
         adjust_enm1<=adjust_en;
         adjust_enm2<=adjust_enm1;
         cmp1_en1<=adjust_enm1 xor adjust_enm2;
         cmp1_en2<=adjust_enm1 xor adjust_enm2;
         cmp1_en3<=adjust_enm1 xor adjust_enm2;
         cmp1_en1m<=adjust_enm1 xor adjust_enm2;
         cmp1_en2m<=adjust_enm1 xor adjust_enm2;
         cmp1_en3m<=adjust_enm1 xor adjust_enm2;
         mult_en3<=cmp1_en3m;
         mult_en3<=cmp1_en3m;
 
         mult_en1m<=cmp1_en1m;
         mult_en2m<=cmp1_en2m;
         mult_en3m<=cmp1_en3m;

         cmp2_en1<=mult_en1m;
         cmp2_en2<=mult_en2m;
cmp2_en3<=mult_en3m;


 cmp2_en1m<=mult_en1m;
           cmp2_en2m<=mult_en2m;
           cmp2_en3m<=mult_en3m;
           addrgene_en1<=cmp2_en1m;
           addrgene_en2<=cmp2_en2m;
           addrgene_en3<=cmp2_en3m;
      end if;
     end process;
 end rtl;