store.vhd

来自「用VHDL编写的由FPGA控制SDRAM的存储控制程序」· VHDL 代码 · 共 66 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity store is
	port(   datain : in std_logic_vector(31 downto 0);
			   clk : in std_logic;
			  stop : in std_logic;
			 reset : in std_logic;
				rw : in std_logic;
		   dataout : out std_logic_vector(31 downto 0);
			  addr : out std_logic_vector(17 downto 0);
			  ce_n : out std_logic;
			  we_n : out std_logic;
			 ready : out std_logic
		 );
end entity;

architecture arch_store of store is
	signal addr_cache : std_logic_vector(17 downto 0) :=
							"000000000000000000";
	signal ready_cache : std_logic := '0';
	signal state : integer range 0 to 2 := 0;
begin
	
	ready <= ready_cache; 
	process(clk)
	begin
		if(clk 'event and clk = '1') then
			if(reset = '1') then
				addr_cache <= "000000000000000000";
				ready_cache <= '0';
				state <= 0;
			elsif(reset = '0' and ready_cache = '0' and stop = '0') then
				
				if(state = 0) then
					addr <= addr_cache;
				elsif(state = 1) then
					ce_n <= '0';
					we_n <= rw;
					if(rw = '0') then						
						dataout <= datain;
					end if;
				elsif(state = 2) then
					--if(rw = '1') then
					--	datain <= dataout;
					--end if;
					ce_n <= '1';
					we_n <= '1';
					if(addr_cache = "111111111111111111") then
						ready_cache <= '1';
					else
						addr_cache <= addr_cache + 1;
					end if;
				end if;
				if(state = 2) then state <= 0;
				else state <= state + 1;
				end if;
			elsif(reset = '0' and ready_cache = '0' and stop = '1') then
				state <= 0;
				ce_n <= '1';
				we_n <= '1';
			end if;
		end if;
	end process;
end architecture;