bahe.tan.rpt

来自「设计四 拔河游戏机 1、 设计一个能进行拔河游戏的电路。 2、 电路使用15」· RPT 代码 · 共 239 行 · 第 1/5 页

; Clock Setup: 'clk_4m'        ; N/A                                      ; None          ; 90.09 MHz ( period = 11.100 ns ) ; qp[2]                                                              ; qp[3]                   ; clk_4m     ; clk_4m   ; 0            ;
; Clock Hold: 'clk_4m'         ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; qp[0]                                                              ; lamper[7]               ; clk_4m     ; clk_4m   ; 49           ;
; Total number of failed paths ;                                          ;               ;                                  ;                                                                    ;                         ;            ;          ; 49           ;
+------------------------------+------------------------------------------+---------------+----------------------------------+--------------------------------------------------------------------+-------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPF10K10LC84-3     ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk_4m          ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk_4m'                                                                                                                                                                                                                                                                                                                                                                   ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                 ; To                                                                                   ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 90.09 MHz ( period = 11.100 ns )                    ; qp[2]                                                                                ; qp[3]                                                                                ; clk_4m     ; clk_4m   ; None                        ; None                      ; 8.900 ns                ;
; N/A                                     ; 93.46 MHz ( period = 10.700 ns )                    ; Debunce:u2|\Differential:D0                                                          ; qp[2]                                                                                ; clk_4m     ; clk_4m   ; None                        ; None                      ; 8.500 ns                ;
; N/A                                     ; 93.46 MHz ( period = 10.700 ns )                    ; Debunce:u2|\Differential:D1                                                          ; qp[2]                                                                                ; clk_4m     ; clk_4m   ; None                        ; None                      ; 8.500 ns                ;