📄 bahe.map.rpt
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+------------------------+-------------------+-----------------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 15 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; FLEX10K ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+-----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: Debunce:u2|lpm_counter:\Free_Counter:Q[0]_rtl_4 ;
+------------------------+-------------------+-----------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------------+-----------------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 15 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; FLEX10K ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+-----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: Debunce:u1|lpm_counter:\Free_Counter:Q[0]_rtl_5 ;
+------------------------+-------------------+-----------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------------+-----------------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 15 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; FLEX10K ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+-----------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/EDA/拔河游戏机/bahe/bahe.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Web Edition
Info: Processing started: Mon May 22 23:52:32 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off bahe -c bahe
Info: Found 2 design units, including 1 entities, in source file bahe.vhd
Info: Found design unit 1: bahe-bahe_a
Info: Found entity 1: bahe
Info: Found 2 design units, including 1 entities, in source file Debunce.vhd
Info: Found design unit 1: Debunce-a
Info: Found entity 1: Debunce
Info: Found 2 design units, including 1 entities, in source file counter.vhd
Info: Found design unit 1: counter-a
Info: Found entity 1: counter
Info: Elaborating entity "bahe" for the top level hierarchy
Info (10035): Verilog HDL or VHDL information at bahe.vhd(36): object "na" declared but not used
Info (10035): Verilog HDL or VHDL information at bahe.vhd(36): object "nb" declared but not used
Warning (10036): Verilog HDL or VHDL warning at bahe.vhd(36): object "clk" assigned a value but never read
Info (10035): Verilog HDL or VHDL information at bahe.vhd(40): object "allen" declared but not used
Warning (10492): VHDL Process Statement warning at bahe.vhd(91): signal "clr" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at bahe.vhd(91): signal "judgerr" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at bahe.vhd(91): signal "b" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10631): VHDL Process Statement warning at bahe.vhd(102): signal or variable "lamper" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "lamper" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning (10036): Verilog HDL or VHDL warning at bahe.vhd(131): object "DLY" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at bahe.vhd(131): object "SDLY" assigned a value but never read
Warning (10492): VHDL Process Statement warning at bahe.vhd(162): signal "num" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info (10425): VHDL Case Statement information at bahe.vhd(162): OTHERS choice is never selected
Info: Elaborating entity "Debunce" for hierarchy "Debunce:u1"
Info: Elaborating entity "counter" for hierarchy "counter:u5"
Info (10035): Verilog HDL or VHDL information at counter.vhd(19): object "DLY" declared but not used
Info: Inferred 6 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=25) from the following logic: "\Free_Counter:Q[0]~0"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "counter:u5|Q[0]~0"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "counter:u6|Q[0]~0"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=15) from the following logic: "Debunce:u3|\Free_Counter:Q[0]~0"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=15) from the following logic: "Debunce:u2|\Free_Counter:Q[0]~0"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=15) from the following logic: "Debunce:u1|\Free_Counter:Q[0]~0"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51sp2/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51sp2/libraries/megafunctions/alt_counter_f10ke.tdf
Info: Found entity 1: alt_counter_f10ke
Warning: Latch lamper[1] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal qp[2]
Warning: Latch lamper[2] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal qp[2]
Warning: Latch lamper[3] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal qp[1]
Warning: Latch lamper[4] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal qp[2]
Warning: Latch lamper[5] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal qp[2]
Warning: Latch lamper[6] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal qp[2]
Warning: Latch lamper[7] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal qp[2]
Warning: Latch lamper[8] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal qp[2]
Warning: Latch lamper[9] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal qp[2]
Warning: Latch lamper[10] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal qp[2]
Warning: Latch lamper[11] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal qp[2]
Warning: Latch lamper[12] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal qp[2]
Warning: Latch lamper[13] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal qp[2]
Info: Registers with preset signals will power-up high
Info: Implemented 187 device resources after synthesis - the final resource count might be different
Info: Implemented 5 input pins
Info: Implemented 23 output pins
Info: Implemented 159 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 34 warnings
Info: Processing ended: Mon May 22 23:52:54 2006
Info: Elapsed time: 00:00:23
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