📄 bahe.tan.talkback.xml
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<!--
This XML file (created on Mon May 22 23:53:55 2006) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature. To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder. For more information, go
to www.altera.com/products/software/download/dnl-download_license.html
-->
<talkback>
<ver>5.1</ver>
<schema>quartus_version_5.1_build_216.xsd</schema><license>
<nic_id>000c76594cd8</nic_id>
<cdrive_id>7886784f</cdrive_id>
</license>
<tool>
<name>Quartus II</name>
<version>5.1</version>
<build>Build 216</build>
<service_pack_label>2</service_pack_label>
<binary_type>32</binary_type>
<module>quartus_tan.exe</module>
<edition>Web Edition</edition>
<eval>Eval</eval>
<compilation_end_time>Mon May 22 23:53:56 2006</compilation_end_time>
</tool>
<machine>
<os>Windows XP</os>
<cpu>
<proc_count>1</proc_count>
<cpu_freq units="MHz">2019</cpu_freq>
</cpu>
<ram units="MB">224</ram>
</machine>
<top_file>F:/EDA/拔河游戏机/bahe/bahe</top_file>
<compilation_summary>
<flow_status>Successful - Mon May 22 23:53:55 2006</flow_status>
<quartus_ii_version>5.1 Build 216 03/06/2006 SP 2 SJ Web Edition</quartus_ii_version>
<revision_name>bahe</revision_name>
<top_level_entity_name>bahe</top_level_entity_name>
<family>FLEX10K</family>
<met_timing_requirements>No</met_timing_requirements>
<total_logic_elements>160 / 576 ( 28 % )</total_logic_elements>
<total_pins>28 / 59 ( 47 % )</total_pins>
<total_memory_bits>0 / 6,144 ( 0 % )</total_memory_bits>
<device>EPF10K10LC84-3</device>
<timing_models>Final</timing_models>
</compilation_summary>
<compile_id>F6E1164</compile_id>
<mep_data>
<command_line>quartus_tan --read_settings_files=off --write_settings_files=off bahe -c bahe</command_line>
</mep_data>
<software_data>
<smart_recompile>off</smart_recompile>
</software_data>
<messages>
<warning>Warning: Circuit may not operate. Detected 49 non-operational path(s) clocked by clock "clk_4m" with clock skew larger than data delay. See Compilation Report for details.</warning>
<warning>Warning: Found 7 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew</warning>
<warning>Warning: Found pins functioning as undefined clocks and/or memory enables</warning>
<warning>Warning: Timing Analysis is analyzing one or more combinational loops as latches</warning>
<warning>Warning: Node "lamper[13]" is a latch</warning>
<info>Info: Quartus II Timing Analyzer was successful. 0 errors, 20 warnings</info>
<info>Info: Elapsed time: 00:00:05</info>
<info>Info: Processing ended: Mon May 22 23:53:55 2006</info>
<info>Info: th for register "Debunce:u2|\Debounce:D0" (data pin = "man_right", clock pin = "clk_4m") is 1.000 ns</info>
<info>Info: - Shortest pin to register delay is 4.300 ns</info>
</messages>
<clock_settings_summary>
<row>
<clock_node_name>clk_4m</clock_node_name>
<type>User Pin</type>
<fmax_requirement>None</fmax_requirement>
<early_latency units="ns">0.000</early_latency>
<late_latency units="ns">0.000</late_latency>
<multiply_base_fmax_by>N/A</multiply_base_fmax_by>
<divide_base_fmax_by>N/A</divide_base_fmax_by>
<offset>N/A</offset>
</row>
</clock_settings_summary>
<performance>
<nonclk>
<type>Worst-case tsu</type>
<slack>N/A</slack>
<required>None</required>
<actual>8.200 ns</actual>
</nonclk>
<nonclk>
<type>Worst-case tco</type>
<slack>N/A</slack>
<required>None</required>
<actual>31.300 ns</actual>
</nonclk>
<nonclk>
<type>Worst-case th</type>
<slack>N/A</slack>
<required>None</required>
<actual>1.000 ns</actual>
</nonclk>
<clk>
<name>clk_4m</name>
<slack>N/A</slack>
<required>None</required>
<actual>90.09 MHz ( period = 11.100 ns )</actual>
</clk>
</performance>
<compile_id>8050E634</compile_id>
</talkback>
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