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ISE Auto-Make Log File
-----------------------

Updating: Generate Programming File

Starting: 'exewrap @__ednTOngd_exewrap.rsp'


Starting: 'ngdbuild -f __ngdbuild.rsp '


Release 4.1WP3.x - ngdbuild E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
ERROR:Portability:138 - Invalid file format, check the command argument file
   "__ngdbuild.rsp".
Usage: ngdbuild [-p <partname>] {-sd <source_dir>} {-l <library>} [-ur
<rules_file[.urf]>] [-dd <output_dir>] [-r] [-a] [-u] [-nt timestamp|on|off]
[-uc <ucf_file[.ucf]>] [-aul] [-i] [-modular initial|module|assemble] [-quiet]
[-verbose] [-active <active_module_name>] [-pimpath <pimpath>] {-use_pim
<pim_module_name>} <design_name> [<ngd_file[.ngd]>]

      -p  partname     Use specified part type to implement the design
      -sd source_dir   Add "source_dir" to the list of directories
                       to search when resolving netlist file references
      -l library       Add "library" to the list of source libraries
                       passed to the netlisters
      -ur rules_file   User rules file for netlist launcher
      -dd output_dir   Directory to place intermediate .ngo files
      -nt value        NGO file generation
                       Options:       "timestamp", "on", "off"
                       -nt timestamp: Regenerate NGO only when source
                                      netlist is newer than existing
                                      NGO file (default)
                       -nt on:        Always regenerate NGO file from
                                      source design netlists
                       -nt off:       Do not regenerate NGO files
                                      which already exist. Build NGD
                                      file from existing NGO files
      -uc ucf_file     Use specified "User Constraint File".
                       The file <design_name>.ucf is used by default
                       if it is found in the local directory.
      -r               Ignore location constraints
      -aul             Allow unmatched LOC constraints
      -a               Infer pad components from ports in top-level EDIF
                       netlist (if any)
      -i               Ignore usage of default ucf file, if present
      -u               Allow unexpanded blocks in output NGD design.
                       During partial design assembly flow, it gets used
                       along with -modular assemble switch to consider
                       unexpanded blocks as unimplemented modules.
      -modular initial|module|assemble
                       Modular design flows:
         -modular initial
                       Modular design in initial budgeting mode
         -modular module -active <active_module_name>
                       Modular design in active module mode
            -active <active_module_name>
                       Specifies the name of active module.
         -modular assemble -pimpath <pimpath> -use_pim <pim_module_name>
                       Modular design in assembly mode
            -pimpath <pimpath>
                       Specifies directory contains PIMs.
            -use_pim <pim_module_name>
                       Specifies an instantiated module in a top level design.
                       -use_pim can be used multiple times to specify multiple 
                       instantiated modules.
                       if -use_pim is missing, all subdirectories located in 
                       <pimpath> directory, which contain a .ngo file with the 
                       same subdirectory name, will be considered as valid 
                       instantiated modules.
      -quiet           Only report Warning and Error messages
      -verbose         Reports all messages
NGDBUILD:  Translates and merges the various source files of a design into a
single "NGD" design database.
EXEWRAP detected a return code of '2' from program 'ngdbuild'

Done: failed with exit code: 0002.

Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "buzz.v"
Module <buzz> compiled
No errors in compilation
Analysis of file <buzz.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <buzz>.
Module <buzz> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <buzz>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <buzz>.
    Related source file is buzz.v.
WARNING:Xst:737 - Found 1-bit latch for signal <buzzout_reg>.
    Found 31-bit up counter for signal <counter>.
    Summary:
	inferred   1 Counter(s).
Unit <buzz> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 1
 31-bit up counter                 : 1
# Latches                          : 1
 1-bit latch                       : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <counter_30> is unconnected in block <buzz>.
WARNING:Xst:1291 - FF/Latch <counter_28> is unconnected in block <buzz>.
WARNING:Xst:1291 - FF/Latch <counter_29> is unconnected in block <buzz>.

Optimizing unit <buzz> ...
Loading device for application Xst from file 'v100.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block buzz, actual ratio is 1.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100pq208-5 

 Number of Slices:                      16  out of   1200     1%  
 Number of Slice Flip Flops:            29  out of   2400     1%  
 Number of 4 input LUTs:                29  out of   2400     1%  
 Number of bonded IOBs:                  1  out of    144     0%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
counter_27:Q                       | NONE                   | 1     |
clk                                | BUFGP                  | 28    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 6.432ns (Maximum Frequency: 155.473MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 8.128ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\fpga\xilins2board\example\buzz/_ngo
-i -p xc2s100-pq208-5 buzz.ngc buzz.ngd 

Reading NGO file "D:/fpga/xilins2board/Example/buzz/buzz.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 39400 kilobytes

Writing NGD file "buzz.ngd" ...

Writing NGDBUILD log file "buzz.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s100pq208-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        28 out of  2,400    1%
  Number of 4 input LUTs:             2 out of  2,400    1%
Logic Distribution:
    Number of occupied Slices:                          15 out of  1,200    1%
    Number of Slices containing only related logic:     15 out of     15  100%
    Number of Slices containing unrelated logic:         0 out of     15    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:           29 out of  2,400    1%
      Number used as logic:                         2
      Number used as a route-thru:                 27
   Number of bonded IOBs:             1 out of    140    1%
      IOB Latches:                                  1
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  403
Additional JTAG gate count for IOBs:  96
Peak Memory Usage:  60 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "buzz_map.mrp" for details.
Completed process "Map".

Mapping Module buzz . . .
MAP command line:
map -intstyle ise -p xc2s100-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o buzz_map.ncd buzz.ngd buzz.pcf
Mapping Module buzz: DONE



Started process "Place & Route".





Constraints file: buzz.pcf

Loading device database for application Par from file "buzz_map.ncd".
   "buzz" is an NCD, version 2.38, device xc2s100, package pq208, speed -5
Loading device for application Par from file 'v100.nph' in environment
C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2004-06-25.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs             1 out of 140     1%
      Number of LOCed External IOBs    0 out of 1       0%

   Number of SLICEs                   15 out of 1200    1%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989698) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
........
Phase 5.8 (Checksum:98bdc1) REAL time: 0 secs