__projnav.log

7段发光二极管vhdl程序

ISE Auto-Make Log File
-----------------------

Updating: Generate PROM File

Starting: 'exewrap @__ednTOngd_exewrap.rsp'


Starting: 'ngdbuild -f __ngdbuild.rsp '


Release 4.2WP3.x - ngdbuild E.38
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -dd
f:/zhiyuan/dp_series/dp-fpga/dp-fpga-cd/example/7led/_ngo -nt timestamp -p
xc2s100-pq208-5 dled.ngc dled.ngd 

Reading NGO file "F:/zhiyuan/DP_series/DP-FPGA/DP-FPGA-CD/Example/7led/dled.ngc"
...
Reading component libraries for design expansion...

Annotating constraints to design from file "dled.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "dled.ngd" ...

Writing NGDBUILD log file "dled.bld"...

NGDBUILD done.
EXEWRAP detected that program 'ngdbuild' completed successfully.

Done: completed successfully.

Starting: 'exewrap @_ngdTOnc1_exewrap.rsp'


Creating TCL Process
Starting: 'map -f _map.rsp'


Release 4.2WP3.x - Map E.38
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
Using target part "2s100pq208-5".
Removing unused or disabled logic...
Running cover...
Writing file dled.ngm...
Running directed packing...
Running delay-based packing...
Running related packing...
Writing design file "dled.ncd"...

Design Summary:
   Number of errors:      0
   Number of warnings:    0
   Number of Slices:                 31 out of  1,200    2%
   Number of Slices containing
      unrelated logic:                0 out of     31    0%
   Number of Slice Flip Flops:       42 out of  2,400    1%
   Total Number 4 input LUTs:        42 out of  2,400    1%
      Number used as LUTs:                         21
      Number used as a route-thru:                 21
   Number of bonded IOBs:            12 out of    140    8%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%
Total equivalent gate count for design:  714
Additional JTAG gate count for IOBs:  624

Mapping completed.
See MAP report file "dled.mrp" for details.
Tcl C:/xilinx_webpack/data/projnav/_map.tcl detected that program 'map -f _map.rsp' completed successfully.

Done: completed successfully.

Starting: 'exewrap @_nc1TOncd_exewrap.rsp'


Creating TCL Process
Found _prepar.rsp
Starting: 'par -f _par.rsp'


Release 4.2WP3.x - Par E.38
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.


WARNING:Par:69 - Option "-xe" overrides some effects of "-ol".


Constraints file: dled.pcf

Loading design for application par from file par_temp.ncd.
   "dled" is an NCD, version 2.37, device xc2s100, package pq208, speed -5
Loading device for application par from file 'v100.nph' in environment
C:/xilinx_webpack.
Device speed data version:  PRELIMINARY 1.23 2001-12-19.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            12 out of 140     8%
      Number of LOCed External IOBs   12 out of 12    100%

   Number of SLICEs                   31 out of 1200    2%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)
Extra effort level (-xe):     0 (set by user)

Starting the placer. REAL time: 2 secs 
Placement pass 1 .
Placer score = 2250
Placement pass 2 .
Placer score = 2325
Optimizing ... 
Placer score = 1920
All IOBs have been constrained to specific sites.
Placer completed in real time: 2 secs 

Dumping design to file dled.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 2 secs 

0 connection(s) routed; 158 unrouted active, 4 unrouted PWR/GND.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 2 secs 
Starting iterative routing. 
Routing active signals.
....
End of iteration 1 
162 successful; 0 unrouted; (0) REAL time: 3 secs 
Constraints are met. 
Total REAL time: 3 secs 
Total CPU  time: 2 secs 
End of route.  162 routed (100.00%); 0 unrouted.
No errors found. 
Completely routed. 

This design was run without timing constraints.  It is likely that much better
circuit performance can be obtained by trying either or both of the following:

  - Enabling the Delay Based Cleanup router pass, if not already enabled
  - Supplying timing constraints in the input design


Total REAL time to Router completion: 3 secs 
Total CPU time to Router completion: 2 secs 

Generating PAR statistics.
Dumping design to file dled.ncd.


All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 3 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.

PAR done.
Tcl C:/xilinx_webpack/data/projnav/_par.tcl detected that program 'par -f _par.rsp' completed successfully.

PAR completed successfully
Done: completed successfully.

Starting: 'exewrap -tcl -command C:/xilinx_webpack/data/projnav/_bitgen.tcl bitgen.rsp dled'


Done: completed successfully.

Starting: 'exewrap -tapkeep -tcl -command C:/xilinx_webpack/data/projnav/_utTObit.tcl dled'


Creating TCL Process
Starting: 'bitgen -f dled.ut dled.ncd'


Release 4.2WP3.x - Bitgen E.38
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.

Loading design for application Bitgen from file dled.ncd.
   "dled" is an NCD, version 2.37, device xc2s100, package pq208, speed -5
Loading device for application Bitgen from file 'v100.nph' in environment
C:/xilinx_webpack.
Opened constraints file dled.pcf.

Mon Mar 10 15:13:53 2003

Running DRC.
DRC detected 0 errors and 0 warnings.
Creating bit map...
Saving bit stream in "dled.bit".
Bitstream generation is complete.
Tcl C:/xilinx_webpack/data/projnav/_utTObit.tcl detected that program 'bitgen -f dled.ut dled.ncd' completed successfully.


Done: completed successfully.

Launching: 'exewrap -tcl -command __launchPromFmtr.tcl'



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "dled.v"
Module <dled> compiled
No errors in compilation
Analysis of file <dled.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <dled>.
WARNING:Xst:905 - dled.v line 23: The signals <disp_buf> are missing in the sensitivity list of always block.
Module <dled> is correct for synthesis.
 
    Set property "resynthesize = true" for unit <dled>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <dled>.
    Related source file is dled.v.
    Found 16x8-bit ROM for signal <seg_reg>.
    Found 26-bit up counter for signal <count>.
    Found 16-bit up counter for signal <disp_buf>.
    Found 4-bit 4-to-1 multiplexer for signal <disp_dat>.
    Summary:
	inferred   1 ROM(s).
	inferred   2 Counter(s).
	inferred   4 Multiplexer(s).
Unit <dled> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 16x8-bit ROM                      : 1
# Counters                         : 2
 26-bit up counter                 : 1
 16-bit up counter                 : 1
# Multiplexers                     : 1
 4-bit 4-to-1 multiplexer          : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <dled> ...
Loading device for application Xst from file 'v100.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block dled, actual ratio is 2.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100pq208-5 

 Number of Slices:                      33  out of   1200     2%  
 Number of Slice Flip Flops:            42  out of   2400     1%  
 Number of 4 input LUTs:                61  out of   2400     2%  
 Number of bonded IOBs:                 12  out of    144     8%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 26    |
count_25:Q                         | NONE                   | 16    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 6.982ns (Maximum Frequency: 143.225MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 14.130ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\fpga\xilins2board\example\7led/_ngo
-i -p xc2s100-pq208-5 dled.ngc dled.ngd 

Reading NGO file "D:/fpga/xilins2board/Example/7led/dled.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 39400 kilobytes

Writing NGD file "dled.ngd" ...

Writing NGDBUILD log file "dled.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s100pq208-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:        42 out of  2,400    1%
  Number of 4 input LUTs:            21 out of  2,400    1%
Logic Distribution:
    Number of occupied Slices:                          31 out of  1,200    2%
    Number of Slices containing only related logic:     31 out of     31  100%
    Number of Slices containing unrelated logic:         0 out of     31    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:           61 out of  2,400    2%
      Number used as logic:                        21
      Number used as a route-thru:                 40
   Number of bonded IOBs:            12 out of    140    8%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  714
Additional JTAG gate count for IOBs:  624
Peak Memory Usage:  60 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are