dled.syr

7段发光二极管vhdl程序

# Adders/Subtractors               : 2
#      26-bit adder                : 2

Cell Usage :
# BELS                             : 144
#      GND                         : 1
#      LUT1                        : 1
#      LUT1_D                      : 1
#      LUT1_L                      : 39
#      LUT2                        : 4
#      LUT3                        : 8
#      LUT4                        : 7
#      MUXCY                       : 39
#      MUXF5                       : 4
#      VCC                         : 1
#      XORCY                       : 39
# FlipFlops/Latches                : 41
#      FD                          : 41
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 12
#      OBUF                        : 12
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s100pq208-5 

 Number of Slices:                      32  out of   1200     2%  
 Number of Slice Flip Flops:            41  out of   2400     1%  
 Number of 4 input LUTs:                60  out of   2400     2%  
 Number of bonded IOBs:                 12  out of    144     8%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 25    |
count_24:Q                         | NONE                   | 16    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 6.932ns (Maximum Frequency: 144.258MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 14.130ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               6.932ns (Levels of Logic = 12)
  Source:            count_14 (FF)
  Destination:       count_24 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: count_14 to count_24
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q              13   1.292   2.500  count_14 (count_14)
     LUT1_L:I0->LO         1   0.653   0.000  count<14>_rt (count<14>_rt)
     MUXCY:S->O            1   0.784   0.000  count_LPM_COUNTER_2__n0000<14>cy (count_LPM_COUNTER_2__n0000<14>_cyo)
     MUXCY:CI->O           1   0.050   0.000  count_LPM_COUNTER_2__n0000<15>cy (count_LPM_COUNTER_2__n0000<15>_cyo)
     MUXCY:CI->O           1   0.050   0.000  count_LPM_COUNTER_2__n0000<16>cy (count_LPM_COUNTER_2__n0000<16>_cyo)
     MUXCY:CI->O           1   0.050   0.000  count_LPM_COUNTER_2__n0000<17>cy (count_LPM_COUNTER_2__n0000<17>_cyo)
     MUXCY:CI->O           1   0.050   0.000  count_LPM_COUNTER_2__n0000<18>cy (count_LPM_COUNTER_2__n0000<18>_cyo)
     MUXCY:CI->O           1   0.050   0.000  count_LPM_COUNTER_2__n0000<19>cy (count_LPM_COUNTER_2__n0000<19>_cyo)
     MUXCY:CI->O           1   0.050   0.000  count_LPM_COUNTER_2__n0000<20>cy (count_LPM_COUNTER_2__n0000<20>_cyo)
     MUXCY:CI->O           1   0.050   0.000  count_LPM_COUNTER_2__n0000<21>cy (count_LPM_COUNTER_2__n0000<21>_cyo)
     MUXCY:CI->O           1   0.050   0.000  count_LPM_COUNTER_2__n0000<22>cy (count_LPM_COUNTER_2__n0000<22>_cyo)
     MUXCY:CI->O           0   0.050   0.000  count_LPM_COUNTER_2__n0000<23>cy (count_LPM_COUNTER_2__n0000<23>_cyo)
     XORCY:CI->O           1   0.500   0.000  count_LPM_COUNTER_2__n0000<24>_xor (count__n0000<24>)
     FD:D                      0.753          count_24
    ----------------------------------------
    Total                      6.932ns (4.432ns logic, 2.500ns route)
                                       (63.9% logic, 36.1% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'count_24:Q'
Delay:               6.022ns (Levels of Logic = 17)
  Source:            disp_buf_0 (FF)
  Destination:       disp_buf_15 (FF)
  Source Clock:      count_24:Q rising
  Destination Clock: count_24:Q rising

  Data Path: disp_buf_0 to disp_buf_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   1.292   1.340  disp_buf_0 (disp_buf_0)
     LUT1_L:I0->LO         2   0.653   0.000  disp_buf_LPM_COUNTER_1__n0000<0>lut (disp_buf_N415)
     MUXCY:S->O            1   0.784   0.000  disp_buf_LPM_COUNTER_1__n0000<0>cy (disp_buf_LPM_COUNTER_1__n0000<0>_cyo)
     MUXCY:CI->O           1   0.050   0.000  disp_buf_LPM_COUNTER_1__n0000<1>cy (disp_buf_LPM_COUNTER_1__n0000<1>_cyo)
     MUXCY:CI->O           1   0.050   0.000  disp_buf_LPM_COUNTER_1__n0000<2>cy (disp_buf_LPM_COUNTER_1__n0000<2>_cyo)
     MUXCY:CI->O           1   0.050   0.000  disp_buf_LPM_COUNTER_1__n0000<3>cy (disp_buf_LPM_COUNTER_1__n0000<3>_cyo)
     MUXCY:CI->O           1   0.050   0.000  disp_buf_LPM_COUNTER_1__n0000<4>cy (disp_buf_LPM_COUNTER_1__n0000<4>_cyo)
     MUXCY:CI->O           1   0.050   0.000  disp_buf_LPM_COUNTER_1__n0000<5>cy (disp_buf_LPM_COUNTER_1__n0000<5>_cyo)
     MUXCY:CI->O           1   0.050   0.000  disp_buf_LPM_COUNTER_1__n0000<6>cy (disp_buf_LPM_COUNTER_1__n0000<6>_cyo)
     MUXCY:CI->O           1   0.050   0.000  disp_buf_LPM_COUNTER_1__n0000<7>cy (disp_buf_LPM_COUNTER_1__n0000<7>_cyo)
     MUXCY:CI->O           1   0.050   0.000  disp_buf_LPM_COUNTER_1__n0000<8>cy (disp_buf_LPM_COUNTER_1__n0000<8>_cyo)
     MUXCY:CI->O           1   0.050   0.000  disp_buf_LPM_COUNTER_1__n0000<9>cy (disp_buf_LPM_COUNTER_1__n0000<9>_cyo)
     MUXCY:CI->O           1   0.050   0.000  disp_buf_LPM_COUNTER_1__n0000<10>cy (disp_buf_LPM_COUNTER_1__n0000<10>_cyo)
     MUXCY:CI->O           1   0.050   0.000  disp_buf_LPM_COUNTER_1__n0000<11>cy (disp_buf_LPM_COUNTER_1__n0000<11>_cyo)
     MUXCY:CI->O           1   0.050   0.000  disp_buf_LPM_COUNTER_1__n0000<12>cy (disp_buf_LPM_COUNTER_1__n0000<12>_cyo)
     MUXCY:CI->O           1   0.050   0.000  disp_buf_LPM_COUNTER_1__n0000<13>cy (disp_buf_LPM_COUNTER_1__n0000<13>_cyo)
     MUXCY:CI->O           0   0.050   0.000  disp_buf_LPM_COUNTER_1__n0000<14>cy (disp_buf_LPM_COUNTER_1__n0000<14>_cyo)
     XORCY:CI->O           1   0.500   0.000  disp_buf_LPM_COUNTER_1__n0000<15>_xor (disp_buf__n0000<15>)
     FD:D                      0.753          disp_buf_15
    ----------------------------------------
    Total                      6.022ns (4.682ns logic, 1.340ns route)
                                       (77.7% logic, 22.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              14.130ns (Levels of Logic = 4)
  Source:            count_14 (FF)
  Destination:       seg<6> (PAD)
  Source Clock:      clk rising

  Data Path: count_14 to seg<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q              13   1.292   2.500  count_14 (count_14)
     LUT3:I0->O            1   0.653   0.000  Mmux_disp_dat_inst_mux_f5_2111_F (N1092)
     MUXF5:I0->O           7   0.375   1.950  Mmux_disp_dat_inst_mux_f5_2111 (disp_dat<2>)
     LUT4:I2->O            1   0.653   1.150  Mrom_seg_reg_inst_lut4_01 (seg_0_OBUF)
     OBUF:I->O                 5.557          seg_0_OBUF (seg<0>)
    ----------------------------------------
    Total                     14.130ns (8.530ns logic, 5.600ns route)
                                       (60.4% logic, 39.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'count_24:Q'
Offset:              12.970ns (Levels of Logic = 4)
  Source:            disp_buf_0 (FF)
  Destination:       seg<6> (PAD)
  Source Clock:      count_24:Q rising

  Data Path: disp_buf_0 to seg<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   1.292   1.340  disp_buf_0 (disp_buf_0)
     LUT3:I1->O            1   0.653   0.000  Mmux_disp_dat_inst_mux_f5_0111_F (N1087)
     MUXF5:I0->O           7   0.375   1.950  Mmux_disp_dat_inst_mux_f5_0111 (disp_dat<0>)
     LUT4:I0->O            1   0.653   1.150  Mrom_seg_reg_inst_lut4_01 (seg_0_OBUF)
     OBUF:I->O                 5.557          seg_0_OBUF (seg<0>)
    ----------------------------------------
    Total                     12.970ns (8.530ns logic, 4.440ns route)
                                       (65.8% logic, 34.2% route)

=========================================================================
CPU : 1.91 / 2.91 s | Elapsed : 2.00 / 3.00 s
 
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Total memory usage is 57348 kilobytes