7led.npl

7段发光二极管vhdl程序

JDF G
// Created by Project Navigator ver 1.0
PROJECT 7led
DESIGN 7led
DEVFAM spartan2
DEVFAMTIME 315558000
DEVICE xc2s100
DEVICETIME 315558000
DEVPKG pq208
DEVPKGTIME 315558000
DEVSPEED -5
DEVSPEEDTIME 315558000
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL Verilog
GENERATEDSIMULATIONMODELTIME 0
SOURCE dled.v
DEPASSOC dled dled.ucf
[Normal]
p_impactConfigMode=xstvlg, spartan2, Implementation.t_impactProgrammingTool, 1046313410, Slave Serial
p_ModelSimSimRunTime_tbw=xstvlg, spartan2, Bencher Waveform.t_MSimulateBehavioralVerilogModel, 315558000, 1000ns
xilxBitgStart_Clk=xstvlg, spartan2, Implementation.t_bitFile, 1145698421, JTAG Clock
[STATUS-ALL]
dled.ncdFile=WARNINGS,1145701800
dled.ngcFile=WARNINGS,1145701793
[STRATEGY-LIST]
Normal=True