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<TITLE>The RISC8 Verilog core</TITLE>
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<B><FONT FACE="Arial" SIZE=5><P ALIGN="CENTER">RISC8 Core</P>
</FONT><FONT FACE="Arial"><P ALIGN="CENTER">Version 1.0</P>
</B></FONT><FONT FACE="Times"><P ALIGN="CENTER">Tom Coonan</P>
<P ALIGN="CENTER">tcoonan@mindspring.com</P>
</FONT><FONT SIZE=2><P ALIGN="JUSTIFY">1	Introduction	</FONT><A HREF="#_Toc469736944">*</A> </P>
<FONT SIZE=2><P>2	Quick Start	</FONT><A HREF="#_Toc469736945">*</A></P>
<FONT SIZE=2><P>3	System Architecture	</FONT><A HREF="#_Toc469736946">*</A></P>
<FONT SIZE=2><P>4	Compatibility with Microchip 16C57 Devices	</FONT><A HREF="#_Toc469736947">*</A></P>
<FONT SIZE=2><P>5	Module Hierarchy	</FONT><A HREF="#_Toc469736948">*</A></P>
<FONT SIZE=2><P>6	Synthesis	</FONT><A HREF="#_Toc469736949">*</A></P>
<FONT SIZE=2><P>7	CPU Module	</FONT><A HREF="#_Toc469736950">*</A></P>
<FONT SIZE=2><P>8	Memory Interfaces	</FONT><A HREF="#_Toc469736951">*</A></P>
<FONT SIZE=2><P>9	ALU	</FONT><A HREF="#_Toc469736952">*</A></P>
<FONT SIZE=2><P>10	Instruction Decoder	</FONT><A HREF="#_Toc469736953">*</A></P>
<FONT SIZE=2><P>11	Register File	</FONT><A HREF="#_Toc469736954">*</A></P>
<FONT SIZE=2><P>12	Firmware Development	</FONT><A HREF="#_Toc469736955">*</A></P>
<FONT SIZE=2><P>13	Expansion	</FONT><A HREF="#_Toc469736956">*</A></P>
<FONT SIZE=2><P>14	Test Programs	</FONT><A HREF="#_Toc469736957">*</A></P>
<FONT SIZE=2><P>15	Bugs	</FONT><A HREF="#_Toc469736958">*</A></P>
<B><FONT FACE="Arial" SIZE=4><P> </P>
<P><A NAME="_Toc469736944">1	Introduction</A></P>
</B></FONT><FONT SIZE=2><P>The Free-RISC8 is a Verilog implementation of a simple 8-bit processor. The RISC8 is binary code compatible with the Microchip 16C57 processor. Code may be developed and debugged using tools available from a number of 3<SUP>rd</SUP> Party tool developers. Programs existing for the 16C57 may be ported to the RISC8 for use in an FPGA, etc.</P>
<P>The design is synthesizable and has been used by various people in the past within ASICs as well as FPGAs. The package consists of the following Verilog and C files:</P></FONT>
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<P ALIGN="CENTER"><B><I><FONT SIZE=2>File</B></I></FONT></TD>
<TD WIDTH="86%" VALIGN="TOP">
<B><I><FONT SIZE=2><P ALIGN="CENTER">Description</B></I></FONT></TD>
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<FONT SIZE=2><P>test.v</FONT></TD>
<TD WIDTH="86%" VALIGN="TOP">
<FONT SIZE=2><P>Top-level testbench, including the behavioral Verilog program memory</FONT></TD>
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<TR><TD WIDTH="14%" VALIGN="TOP">
<FONT SIZE=2><P>cpu.v</FONT></TD>
<TD WIDTH="86%" VALIGN="TOP">
<FONT SIZE=2><P>Top-level synthesizable module.</FONT></TD>
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<FONT SIZE=2><P>idec.v</FONT></TD>
<TD WIDTH="86%" VALIGN="TOP">
<FONT SIZE=2><P>The Instruction Decoder. This module is instanced underneath the cpu module.</FONT></TD>
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<FONT SIZE=2><P>alu.v</FONT></TD>
<TD WIDTH="86%" VALIGN="TOP">
<FONT SIZE=2><P>The ALU. This module is instanced underneath the cpu module.</FONT></TD>
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<FONT SIZE=2><P>regs.v</FONT></TD>
<TD WIDTH="86%" VALIGN="TOP">
<FONT SIZE=2><P>The Register File. This module is instanced underneath the cpu module.</FONT></TD>
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<FONT SIZE=2><P>exp.v</FONT></TD>
<TD WIDTH="86%" VALIGN="TOP">
<FONT SIZE=2><P>Optional Expansion Module. This is an example module that shows how an expansion circuit is added onto the design. The module supplied with this release implements a very simple DDS (Direct Digital Synthesis) circuit that is used for the DDS demo.</FONT></TD>
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<FONT SIZE=2><P>dram.v</FONT></TD>
<TD WIDTH="86%" VALIGN="TOP">
<FONT SIZE=2><P>Memory model for Register File 慏抋ta memory (it抯 a Synchronous RAM)</FONT></TD>
</TR>
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<FONT SIZE=2><P>pram.v</FONT></TD>
<TD WIDTH="86%" VALIGN="TOP">
<FONT SIZE=2><P>Memory model for Program Memory 慞抋ta memory (it抯 a Synchronous RAM)</FONT></TD>
</TR>
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<FONT SIZE=2><P>hex2v.c,</P>
<P>hex2v.exe</FONT></TD>
<TD WIDTH="86%" VALIGN="TOP">
<FONT SIZE=2><P>A C program that translates Intel HEX format data into the Verilog $readmemh compatible .ROM file.</FONT></TD>
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<FONT SIZE=2><P>basic.asm, basic.hex,</P>
<P>basic.rom</FONT></TD>
<TD WIDTH="86%" VALIGN="TOP">
<FONT SIZE=2><P>The "Basic Confidence" test program which exercises all the instructions.</FONT></TD>
</TR>
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<FONT SIZE=2><P>dds.asm,</P>
<P>dds.hex,</P>
<P>dds.rom</FONT></TD>
<TD WIDTH="86%" VALIGN="TOP">
<FONT SIZE=2><P>A demo that uses the DDS circuit. The demo outputs an FSK "burst".</FONT></TD>
</TR>
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<FONT SIZE=2><P>runit</FONT></TD>
<TD WIDTH="86%" VALIGN="TOP">
<FONT SIZE=2><P>A script containing the Verilog command line required.</FONT></TD>
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<FONT SIZE=2><P>risc8.pdf</FONT></TD>
<TD WIDTH="86%" VALIGN="TOP">
<FONT SIZE=2><P>This file.</FONT></TD>
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<FONT SIZE=2><P> </P>
</FONT><B><FONT FACE="Arial" SIZE=4><P><A NAME="_Toc469736945">2	Quick Start</A></P>
</B></FONT><FONT SIZE=2><P>Extract all the files from the supplied ZIP into a new directory. Once all the files have been extracted from the archive, invoke your Verilog simulator specifying all the Verilog files (the 憆unit⌨️ 快捷键说明
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