📄 car.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_unsigned.all;
ENTITY car IS
PORT(
CLK : IN STD_LOGIC;
left,right : IN STD_LOGIC;
lamp_left : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
lamp_right : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END car;
ARCHITECTURE car_body OF car IS
SIGNAL ltmp : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL rtmp : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
COUNT:
PROCESS(CLK)
--VARIABLE __variable_name : STD_LOGIC;
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF left='1' THEN
IF ltmp="000" THEN
ltmp(0)<='1';
ELSE ltmp(1)<=ltmp(0);ltmp(2)<=ltmp(1);ltmp(0)<=ltmp(2);
END IF;
ELSE ltmp<="000";
END IF;
IF right='1' THEN
IF rtmp="000" THEN
rtmp(0)<='1';
ELSE rtmp(1)<=rtmp(0);rtmp(2)<=rtmp(1);rtmp(0)<=rtmp(2);
END IF;
ELSE rtmp<="000";
END IF;
END IF;
lamp_left<=ltmp;
lamp_right<=rtmp;
END PROCESS COUNT;
END car_body;
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