fir31.vhd

设计一个线性相位FIR滤波器（31阶） 输入8位

library work;
use work.nine_bit_int.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
entity fir31 is
port(r,clk,clk_out:in std_logic;
      xin: in std_logic_vector(7 downto 0);
     y  : out integer range -128 to 127);
       
END;
architecture rtl of fir31 is
component dff1
port( r,clk:in std_logic;
      din:in std_logic_vector(7 downto 0);
      qout:out std_logic_vector(7 downto 0));
end component; 
component mul
port(clk:in std_logic;
      x:in byte;
      a: in std_logic_vector(7 downto 0);
      y:out twobytes);
 end component;
subtype dout1 is std_logic_vector(7 downto 0);
type dout2 is array(0 to 30)of dout1;
signal dout:dout2;
signal addout1:std_logic_vector(8 downto 0);
signal addout1_1:integer range -256 to 255;
signal addout2_2:integer range -256 to 255;
signal addout2:std_logic_vector(8 downto 0);
signal addout3_3:integer range -256 to 255;
signal addout3:std_logic_vector(8 downto 0);
signal addout4_4:integer range -256 to 255;
signal addout4:std_logic_vector(8 downto 0);
signal addout5_5:integer range -256 to 255;
signal addout5:std_logic_vector(8 downto 0);
signal addout6_6:integer range -256 to 255;
signal addout6:std_logic_vector(8 downto 0);
signal addout7:std_logic_vector(8 downto 0);
signal addout7_7:integer range -256 to 255;
signal addout8:std_logic_vector(8 downto 0);
signal addout8_8:integer range -256 to 255;
signal addout9:std_logic_vector(8 downto 0);
signal addout9_9:integer range -256 to 255;
signal addout10:std_logic_vector(8 downto 0);
signal addout10_10:integer range -256 to 255;
signal addout11:std_logic_vector(8 downto 0);
signal addout11_11:integer range -256 to 255;
signal addout12:std_logic_vector(8 downto 0);
signal addout12_12:integer range -256 to 255;
signal addout13:std_logic_vector(8 downto 0);
signal addout13_13:integer range -256 to 255;
signal addout14:std_logic_vector(8 downto 0);
signal addout14_14:integer range -256 to 255;
signal addout15:std_logic_vector(8 downto 0);
signal addout15_15:integer range -256 to 255;
constant addout15_1:std_logic_vector(8 downto 0):="000000000";
signal cxout1: integer range -131072 to 131071;
signal cxout2: integer range -131072 to 131071;
signal cxout3: integer range -131072 to 131071;
signal cxout4: integer range -131072 to 131071;
signal cxout5: integer range -131072 to 131071;
signal cxout6: integer range -131072 to 131071;
signal cxout7: integer range -131072 to 131071;
signal cxout8: integer range -131072 to 131071;
signal cxout9: integer range -131072 to 131071;
signal cxout10: integer range -131072 to 131071;
signal cxout11: integer range -131072 to 131071;
signal cxout12: integer range -131072 to 131071;
signal cxout13: integer range -131072 to 131071;
signal cxout14: integer range -131072 to 131071;
signal cxout15: integer range -131072 to 131071;
constant dcxout15:integer:=0;
signal cxout15_1: integer range -131072 to 131071;
signal cxout15_2: integer range -131072 to 131071;
signal cxout15_3: integer range -131072 to 131071;
signal cxout15_4: integer range -131072 to 131071;
signal cxout1_2:integer range -131072 to 131071;
signal cxout3_4: integer range -131072 to 131071;
signal cxout5_6: integer range -131072 to 131071;
signal cxout7_8: integer range -131072 to 131071;
signal cxout9_10: integer range -131072 to 131071;
signal cxout11_12: integer range -131072 to 131071;
signal cxout13_14: integer range -131072 to 131071;
signal cxout1_4:integer range -131072 to 131071;
signal cxout5_8:integer range -131072 to 131071;
signal cxout9_12:integer range -131072 to 131071;
signal dcxout13_14:integer range -131072 to 131071;
signal cxout1_8: integer range -131072 to 131071;
signal cxout9_14:integer range -131072 to 131071;
signal fout1:integer range -131072 to 131071;
signal fout2:integer range -131072 to 131071;
signal fout3:std_logic_vector(17 downto 0) ;
signal fout4:std_logic_vector(10 downto 0) ;

--signal clk_temp: std_logic;
--signal clk_out:std_logic;
begin 
--process(clk)--20分频
 --variable counter: integer range 0 to 15;
 --constant md: integer:=10;
--begin
 --if(clk'event and clk='1') then 
 --if(counter=md) then
  --counter:=0;
--clk_temp<=not clk_temp;
--else
--counter:=counter+1;
--end if;
--end if;
--end process;
--clk_out<=clk_temp;
 
  dout(0)<=xin;
   g1:for i in 0 to 29 generate
   dffx: dff1 port map (r,clk_out,dout(i),dout(i+1));
   end generate;
  
addout1<=conv_std_logic_vector(conv_integer(dout(0)+dout(30)),9);
addout2<=conv_std_logic_vector(conv_integer(dout(1)+dout(29)),9);
addout3<=conv_std_logic_vector(conv_integer(dout(3)+dout(27)),9);
addout4<=conv_std_logic_vector(conv_integer(dout(4)+dout(26)),9);
addout5<=conv_std_logic_vector(conv_integer(dout(5)+dout(25)),9);
addout6<=conv_std_logic_vector(conv_integer(dout(6)+dout(24)),9);
addout7<=conv_std_logic_vector(conv_integer(dout(7)+dout(23)),9);
addout8<=conv_std_logic_vector(conv_integer(dout(8)+dout(22)),9);
addout9<=conv_std_logic_vector(conv_integer(dout(9)+dout(21)),9);
addout10<=conv_std_logic_vector(conv_integer(dout(10)+dout(20)),9);
addout11<=conv_std_logic_vector(conv_integer(dout(11)+dout(19)),9);
addout12<=conv_std_logic_vector(conv_integer(dout(12)+dout(18)),9);
addout13<=conv_std_logic_vector(conv_integer(dout(13)+dout(17)),9);
addout14<=conv_std_logic_vector(conv_integer(dout(14)+dout(16)),9);
addout15<=conv_std_logic_vector(conv_integer(dout(15)+addout15_1),9);
addout1_1<=conv_integer(addout1);
addout2_2<=conv_integer(addout2);
addout3_3<=conv_integer(addout3);
addout4_4<=conv_integer(addout4);
addout5_5<=conv_integer(addout5);
addout6_6<=conv_integer(addout6);
addout7_7<=conv_integer(addout7);
addout8_8<=conv_integer(addout8);
addout9_9<=conv_integer(addout9);
addout10_10<=conv_integer(addout10);
addout11_11<=conv_integer(addout11);
addout12_12<=conv_integer(addout12);
addout13_13<=conv_integer(addout13);
addout14_14<=conv_integer(addout14);
addout15_15<=conv_integer(addout15);

u1: mul port map(clk,addout1_1,"00000001",cxout1);
u2: mul port map(clk,addout2_2,"00000010",cxout2);
u3: mul port map(clk,addout3_3,"00000010",cxout3);
u4: mul port map(clk,addout4_4,"00000010",cxout4);
u5: mul port map(clk,addout5_5,"00000001",cxout5);
u6: mul port map(clk,addout6_6,"00000110",cxout6);
u7: mul port map(clk,addout7_7,"00000110",cxout7);
u8: mul port map(clk,addout8_8,"00000001",cxout8);
u9: mul port map(clk,addout9_9,"00001101",cxout9);
u10: mul port map(clk,addout10_10,"00010101",cxout10);
u11: mul port map(clk,addout11_11,"00001011",cxout11);
u12: mul port map(clk,addout12_12,"00010110",cxout12);
u13: mul port map(clk,addout13_13,"01000101",cxout13);
u14: mul port map(clk,addout14_14,"01101111",cxout14);
u15: mul port map(clk,addout15_15,"10000000",cxout15);
cxout1_2<=cxout1+cxout2;
cxout3_4<=cxout3+cxout4;
cxout5_6<=cxout5+cxout6;
cxout7_8<=cxout7-cxout8;
cxout9_10<=cxout9+cxout10;
cxout11_12<=cxout12-cxout11;
cxout13_14<=cxout13+cxout14;
cxout15_1<=cxout15+dcxout15;
cxout1_4<=cxout1_2-cxout3_4;
cxout5_8<=cxout5_6+cxout7_8;
cxout9_12<=cxout11_12-cxout9_10;
dcxout13_14<=cxout13_14+dcxout15;
cxout15_2<=cxout15_1+dcxout15;
cxout1_8<=cxout1_4+cxout5_8;
cxout9_14<=cxout9_12+dcxout13_14;
cxout15_3<=cxout15_2+dcxout15;
fout1<=cxout1_8+cxout9_14;
cxout15_4<=cxout15_3+dcxout15;
fout2<=fout1+cxout15_4;
fout3<=conv_std_logic_vector(fout2,18);
process(clk_out)
begin
if(clk_out'event and clk_out='1') then
fout4<=fout3(17 downto 7);
y<=conv_integer(fout4);
end if;
end process;
end rtl;