📄 fir31.tan.rpt
字号:
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_11_dffx|qout[6]~reg0 ; dff1:g1_12_dffx|qout[6]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_25_dffx|qout[3]~reg0 ; dff1:g1_26_dffx|qout[3]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_3_dffx|qout[7]~reg0 ; dff1:g1_4_dffx|qout[7]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_20_dffx|qout[4]~reg0 ; dff1:g1_21_dffx|qout[4]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_8_dffx|qout[0]~reg0 ; dff1:g1_9_dffx|qout[0]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_2_dffx|qout[3]~reg0 ; dff1:g1_3_dffx|qout[3]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_21_dffx|qout[2]~reg0 ; dff1:g1_22_dffx|qout[2]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_0_dffx|qout[4]~reg0 ; dff1:g1_1_dffx|qout[4]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_2_dffx|qout[7]~reg0 ; dff1:g1_3_dffx|qout[7]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_3_dffx|qout[1]~reg0 ; dff1:g1_4_dffx|qout[1]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_8_dffx|qout[4]~reg0 ; dff1:g1_9_dffx|qout[4]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_18_dffx|qout[5]~reg0 ; dff1:g1_19_dffx|qout[5]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_10_dffx|qout[4]~reg0 ; dff1:g1_11_dffx|qout[4]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_16_dffx|qout[4]~reg0 ; dff1:g1_17_dffx|qout[4]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_10_dffx|qout[7]~reg0 ; dff1:g1_11_dffx|qout[7]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_21_dffx|qout[1]~reg0 ; dff1:g1_22_dffx|qout[1]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_19_dffx|qout[1]~reg0 ; dff1:g1_20_dffx|qout[1]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_10_dffx|qout[0]~reg0 ; dff1:g1_11_dffx|qout[0]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_15_dffx|qout[2]~reg0 ; dff1:g1_16_dffx|qout[2]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_10_dffx|qout[3]~reg0 ; dff1:g1_11_dffx|qout[3]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_25_dffx|qout[7]~reg0 ; dff1:g1_26_dffx|qout[7]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_20_dffx|qout[1]~reg0 ; dff1:g1_21_dffx|qout[1]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_2_dffx|qout[1]~reg0 ; dff1:g1_3_dffx|qout[1]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_19_dffx|qout[3]~reg0 ; dff1:g1_20_dffx|qout[3]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_6_dffx|qout[3]~reg0 ; dff1:g1_7_dffx|qout[3]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_21_dffx|qout[0]~reg0 ; dff1:g1_22_dffx|qout[0]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_19_dffx|qout[7]~reg0 ; dff1:g1_20_dffx|qout[7]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_21_dffx|qout[7]~reg0 ; dff1:g1_22_dffx|qout[7]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_0_dffx|qout[5]~reg0 ; dff1:g1_1_dffx|qout[5]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_20_dffx|qout[5]~reg0 ; dff1:g1_21_dffx|qout[5]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_18_dffx|qout[3]~reg0 ; dff1:g1_19_dffx|qout[3]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_20_dffx|qout[2]~reg0 ; dff1:g1_21_dffx|qout[2]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_20_dffx|qout[6]~reg0 ; dff1:g1_21_dffx|qout[6]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_20_dffx|qout[0]~reg0 ; dff1:g1_21_dffx|qout[0]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_2_dffx|qout[0]~reg0 ; dff1:g1_3_dffx|qout[0]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_16_dffx|qout[7]~reg0 ; dff1:g1_17_dffx|qout[7]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_9_dffx|qout[7]~reg0 ; dff1:g1_10_dffx|qout[7]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_21_dffx|qout[4]~reg0 ; dff1:g1_22_dffx|qout[4]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_20_dffx|qout[3]~reg0 ; dff1:g1_21_dffx|qout[3]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; fout4[6] ; y[6]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_18_dffx|qout[0]~reg0 ; dff1:g1_19_dffx|qout[0]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_28_dffx|qout[0]~reg0 ; dff1:g1_29_dffx|qout[0]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_24_dffx|qout[6]~reg0 ; dff1:g1_25_dffx|qout[6]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_28_dffx|qout[2]~reg0 ; dff1:g1_29_dffx|qout[2]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_0_dffx|qout[3]~reg0 ; dff1:g1_1_dffx|qout[3]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_10_dffx|qout[2]~reg0 ; dff1:g1_11_dffx|qout[2]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_17_dffx|qout[6]~reg0 ; dff1:g1_18_dffx|qout[6]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_15_dffx|qout[7]~reg0 ; dff1:g1_16_dffx|qout[7]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_11_dffx|qout[2]~reg0 ; dff1:g1_12_dffx|qout[2]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; Timing analysis restricted to 200 rows. ; To change the limit use Timing Settings (Assignments menu) ; ; ; ; ; ; ; ;
+-----------------------------------------+------------------------------------------------------------+------------------------------+------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+------------------------------------------------------------+-------------------------+-------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 239.18 MHz ( period = 4.181 ns ) ; mul:u12|states_t[6] ; mul:u12|states_p[11] ; clk ; clk ; None ; None ; None ;
; N/A ; 242.42 MHz ( period = 4.125 ns ) ⌨️ 快捷键说明
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