📄 fir31.tan.rpt
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; Number of paths to report ; 200 ; ; ;
; Number of destination nodes to report ; 10 ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ;
+-------------------------------------------------------+--------------------+------+----+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------
; Type ; Slack ; Required Time ; Actual Time ; From ; To ;
+------------------------+-------+---------------+------------------------------------------------+------------------------------+------------------------------+
; Worst-case tsu ; N/A ; None ; 7.449 ns ; xin[0] ; mul:u1|states_t[14] ;
; Worst-case tco ; N/A ; None ; 7.735 ns ; y[4]~reg0 ; y[4] ;
; Worst-case th ; N/A ; None ; -2.135 ns ; xin[1] ; dff1:g1_0_dffx|qout[1]~reg0 ;
; Worst-case minimum tco ; N/A ; None ; 7.090 ns ; y[7]~reg0 ; y[7] ;
; Clock Setup: 'clk' ; N/A ; None ; 239.18 MHz ( period = 4.181 ns ) ; mul:u12|states_t[6] ; mul:u12|states_p[11] ;
; Clock Setup: 'clk_out' ; N/A ; None ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_23_dffx|qout[0]~reg0 ; dff1:g1_24_dffx|qout[0]~reg0 ;
+------------------------+-------+---------------+------------------------------------------------+------------------------------+------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+---------------------------------------------------------------------------------------------------------------------------------------
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk_out ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
; clk ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk_out' ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+------------------------------------------------------------+------------------------------+------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_27_dffx|qout[1]~reg0 ; dff1:g1_28_dffx|qout[1]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_19_dffx|qout[0]~reg0 ; dff1:g1_20_dffx|qout[0]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_7_dffx|qout[3]~reg0 ; dff1:g1_8_dffx|qout[3]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_17_dffx|qout[2]~reg0 ; dff1:g1_18_dffx|qout[2]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_17_dffx|qout[0]~reg0 ; dff1:g1_18_dffx|qout[0]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_15_dffx|qout[0]~reg0 ; dff1:g1_16_dffx|qout[0]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_12_dffx|qout[0]~reg0 ; dff1:g1_13_dffx|qout[0]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_17_dffx|qout[4]~reg0 ; dff1:g1_18_dffx|qout[4]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_14_dffx|qout[3]~reg0 ; dff1:g1_15_dffx|qout[3]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_3_dffx|qout[3]~reg0 ; dff1:g1_4_dffx|qout[3]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_6_dffx|qout[0]~reg0 ; dff1:g1_7_dffx|qout[0]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_1_dffx|qout[3]~reg0 ; dff1:g1_2_dffx|qout[3]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_6_dffx|qout[5]~reg0 ; dff1:g1_7_dffx|qout[5]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_14_dffx|qout[4]~reg0 ; dff1:g1_15_dffx|qout[4]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_0_dffx|qout[7]~reg0 ; dff1:g1_1_dffx|qout[7]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_3_dffx|qout[6]~reg0 ; dff1:g1_4_dffx|qout[6]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_5_dffx|qout[7]~reg0 ; dff1:g1_6_dffx|qout[7]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_4_dffx|qout[5]~reg0 ; dff1:g1_5_dffx|qout[5]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_6_dffx|qout[7]~reg0 ; dff1:g1_7_dffx|qout[7]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_23_dffx|qout[2]~reg0 ; dff1:g1_24_dffx|qout[2]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_14_dffx|qout[7]~reg0 ; dff1:g1_15_dffx|qout[7]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_14_dffx|qout[6]~reg0 ; dff1:g1_15_dffx|qout[6]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_12_dffx|qout[1]~reg0 ; dff1:g1_13_dffx|qout[1]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_5_dffx|qout[5]~reg0 ; dff1:g1_6_dffx|qout[5]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_5_dffx|qout[4]~reg0 ; dff1:g1_6_dffx|qout[4]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_1_dffx|qout[6]~reg0 ; dff1:g1_2_dffx|qout[6]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
; N/A ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dff1:g1_28_dffx|qout[5]~reg0 ; dff1:g1_29_dffx|qout[5]~reg0 ; clk_out ; clk_out ; None ; None ; None ;
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