fir31.tan.qmsg

设计一个线性相位FIR滤波器（31阶） 输入8位

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk_out y\[7\] y\[7\]~reg0 7.090 ns register " "Info: Minimum tco from clock clk_out to destination pin y\[7\] through register y\[7\]~reg0 is 7.090 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_out source 2.984 ns + Shortest register " "Info: + Shortest clock path from clock clk_out to source register is 2.984 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.771 ns) 0.771 ns clk_out 1 CLK Pin_M26 256 " "Info: 1: + IC(0.000 ns) + CELL(0.771 ns) = 0.771 ns; Loc. = Pin_M26; Fanout = 256; CLK Node = 'clk_out'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "" { clk_out } "NODE_NAME" } } } { "G:/mydesign/fir31/fir31.vhd" "" "" { Text "G:/mydesign/fir31/fir31.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.653 ns) + CELL(0.560 ns) 2.984 ns y\[7\]~reg0 2 REG LC_X44_Y20_N5 1 " "Info: 2: + IC(1.653 ns) + CELL(0.560 ns) = 2.984 ns; Loc. = LC_X44_Y20_N5; Fanout = 1; REG Node = 'y\[7\]~reg0'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.213 ns" { clk_out y[7]~reg0 } "NODE_NAME" } } } { "G:/mydesign/fir31/fir31.vhd" "" "" { Text "G:/mydesign/fir31/fir31.vhd" 188 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.331 ns 44.60 % " "Info: Total cell delay = 1.331 ns ( 44.60 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.653 ns 55.40 % " "Info: Total interconnect delay = 1.653 ns ( 55.40 % )" {  } {  } 0}  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.984 ns" { clk_out y[7]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "G:/mydesign/fir31/fir31.vhd" "" "" { Text "G:/mydesign/fir31/fir31.vhd" 188 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.930 ns + Shortest register pin " "Info: + Shortest register to pin delay is 3.930 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns y\[7\]~reg0 1 REG LC_X44_Y20_N5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X44_Y20_N5; Fanout = 1; REG Node = 'y\[7\]~reg0'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "" { y[7]~reg0 } "NODE_NAME" } } } { "G:/mydesign/fir31/fir31.vhd" "" "" { Text "G:/mydesign/fir31/fir31.vhd" 188 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.430 ns) + CELL(2.500 ns) 3.930 ns y\[7\] 2 PIN Pin_N20 0 " "Info: 2: + IC(1.430 ns) + CELL(2.500 ns) = 3.930 ns; Loc. = Pin_N20; Fanout = 0; PIN Node = 'y\[7\]'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "3.930 ns" { y[7]~reg0 y[7] } "NODE_NAME" } } } { "G:/mydesign/fir31/fir31.vhd" "" "" { Text "G:/mydesign/fir31/fir31.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns 63.61 % " "Info: Total cell delay = 2.500 ns ( 63.61 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.430 ns 36.39 % " "Info: Total interconnect delay = 1.430 ns ( 36.39 % )" {  } {  } 0}  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "3.930 ns" { y[7]~reg0 y[7] } "NODE_NAME" } } }  } 0}  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.984 ns" { clk_out y[7]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "3.930 ns" { y[7]~reg0 y[7] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 21 20:17:55 2005 " "Info: Processing ended: Wed Dec 21 20:17:55 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}