fir31.tan.qmsg

设计一个线性相位FIR滤波器（31阶） 输入8位

{ "Info" "ITDB_TSU_RESULT" "mul:u1\|states_t\[14\] xin\[0\] clk 7.449 ns register " "Info: tsu for register mul:u1\|states_t\[14\] (data pin = xin\[0\], clock pin = clk) is 7.449 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.357 ns + Longest pin register " "Info: + Longest pin to register delay is 10.357 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.976 ns) 0.976 ns xin\[0\] 1 PIN Pin_H16 4 " "Info: 1: + IC(0.000 ns) + CELL(0.976 ns) = 0.976 ns; Loc. = Pin_H16; Fanout = 4; PIN Node = 'xin\[0\]'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "" { xin[0] } "NODE_NAME" } } } { "G:/mydesign/fir31/fir31.vhd" "" "" { Text "G:/mydesign/fir31/fir31.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.565 ns) + CELL(0.451 ns) 5.992 ns i~308COUT1 2 COMB LC_X33_Y24_N0 2 " "Info: 2: + IC(4.565 ns) + CELL(0.451 ns) = 5.992 ns; Loc. = LC_X33_Y24_N0; Fanout = 2; COMB Node = 'i~308COUT1'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "5.016 ns" { xin[0] i~308COUT1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 6.054 ns i~309COUT1 3 COMB LC_X33_Y24_N1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.062 ns) = 6.054 ns; Loc. = LC_X33_Y24_N1; Fanout = 2; COMB Node = 'i~309COUT1'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "0.062 ns" { i~308COUT1 i~309COUT1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 6.116 ns i~310COUT1 4 COMB LC_X33_Y24_N2 2 " "Info: 4: + IC(0.000 ns) + CELL(0.062 ns) = 6.116 ns; Loc. = LC_X33_Y24_N2; Fanout = 2; COMB Node = 'i~310COUT1'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "0.062 ns" { i~309COUT1 i~310COUT1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.062 ns) 6.178 ns i~311COUT1 5 COMB LC_X33_Y24_N3 2 " "Info: 5: + IC(0.000 ns) + CELL(0.062 ns) = 6.178 ns; Loc. = LC_X33_Y24_N3; Fanout = 2; COMB Node = 'i~311COUT1'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "0.062 ns" { i~310COUT1 i~311COUT1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 6.301 ns i~312COUT 6 COMB LC_X33_Y24_N4 3 " "Info: 6: + IC(0.000 ns) + CELL(0.123 ns) = 6.301 ns; Loc. = LC_X33_Y24_N4; Fanout = 3; COMB Node = 'i~312COUT'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "0.123 ns" { i~311COUT1 i~312COUT } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.472 ns) 6.773 ns i~315 7 COMB LC_X33_Y24_N7 1 " "Info: 7: + IC(0.000 ns) + CELL(0.472 ns) = 6.773 ns; Loc. = LC_X33_Y24_N7; Fanout = 1; COMB Node = 'i~315'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "0.472 ns" { i~312COUT i~315 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.614 ns) + CELL(0.213 ns) 8.600 ns i~499 8 COMB LC_X22_Y23_N5 8 " "Info: 8: + IC(1.614 ns) + CELL(0.213 ns) = 8.600 ns; Loc. = LC_X22_Y23_N5; Fanout = 8; COMB Node = 'i~499'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "1.827 ns" { i~315 i~499 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.393 ns) + CELL(0.364 ns) 10.357 ns mul:u1\|states_t\[14\] 9 REG LC_X19_Y21_N2 3 " "Info: 9: + IC(1.393 ns) + CELL(0.364 ns) = 10.357 ns; Loc. = LC_X19_Y21_N2; Fanout = 3; REG Node = 'mul:u1\|states_t\[14\]'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "1.757 ns" { i~499 mul:u1|states_t[14] } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.785 ns 26.89 % " "Info: Total cell delay = 2.785 ns ( 26.89 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.572 ns 73.11 % " "Info: Total interconnect delay = 7.572 ns ( 73.11 % )" {  } {  } 0}  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "10.357 ns" { xin[0] i~308COUT1 i~309COUT1 i~310COUT1 i~311COUT1 i~312COUT i~315 i~499 mul:u1|states_t[14] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.918 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 2.918 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clk 1 CLK Pin_M24 780 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 780; CLK Node = 'clk'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "G:/mydesign/fir31/fir31.vhd" "" "" { Text "G:/mydesign/fir31/fir31.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.696 ns) + CELL(0.560 ns) 2.918 ns mul:u1\|states_t\[14\] 2 REG LC_X19_Y21_N2 3 " "Info: 2: + IC(1.696 ns) + CELL(0.560 ns) = 2.918 ns; Loc. = LC_X19_Y21_N2; Fanout = 3; REG Node = 'mul:u1\|states_t\[14\]'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.256 ns" { clk mul:u1|states_t[14] } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns 41.88 % " "Info: Total cell delay = 1.222 ns ( 41.88 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.696 ns 58.12 % " "Info: Total interconnect delay = 1.696 ns ( 58.12 % )" {  } {  } 0}  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.918 ns" { clk mul:u1|states_t[14] } "NODE_NAME" } } }  } 0}  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "10.357 ns" { xin[0] i~308COUT1 i~309COUT1 i~310COUT1 i~311COUT1 i~312COUT i~315 i~499 mul:u1|states_t[14] } "NODE_NAME" } } } { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.918 ns" { clk mul:u1|states_t[14] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_out y\[4\] y\[4\]~reg0 7.735 ns register " "Info: tco from clock clk_out to destination pin y\[4\] through register y\[4\]~reg0 is 7.735 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_out source 2.984 ns + Longest register " "Info: + Longest clock path from clock clk_out to source register is 2.984 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.771 ns) 0.771 ns clk_out 1 CLK Pin_M26 256 " "Info: 1: + IC(0.000 ns) + CELL(0.771 ns) = 0.771 ns; Loc. = Pin_M26; Fanout = 256; CLK Node = 'clk_out'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "" { clk_out } "NODE_NAME" } } } { "G:/mydesign/fir31/fir31.vhd" "" "" { Text "G:/mydesign/fir31/fir31.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.653 ns) + CELL(0.560 ns) 2.984 ns y\[4\]~reg0 2 REG LC_X41_Y20_N9 1 " "Info: 2: + IC(1.653 ns) + CELL(0.560 ns) = 2.984 ns; Loc. = LC_X41_Y20_N9; Fanout = 1; REG Node = 'y\[4\]~reg0'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.213 ns" { clk_out y[4]~reg0 } "NODE_NAME" } } } { "G:/mydesign/fir31/fir31.vhd" "" "" { Text "G:/mydesign/fir31/fir31.vhd" 188 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.331 ns 44.60 % " "Info: Total cell delay = 1.331 ns ( 44.60 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.653 ns 55.40 % " "Info: Total interconnect delay = 1.653 ns ( 55.40 % )" {  } {  } 0}  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.984 ns" { clk_out y[4]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "G:/mydesign/fir31/fir31.vhd" "" "" { Text "G:/mydesign/fir31/fir31.vhd" 188 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.575 ns + Longest register pin " "Info: + Longest register to pin delay is 4.575 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns y\[4\]~reg0 1 REG LC_X41_Y20_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X41_Y20_N9; Fanout = 1; REG Node = 'y\[4\]~reg0'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "" { y[4]~reg0 } "NODE_NAME" } } } { "G:/mydesign/fir31/fir31.vhd" "" "" { Text "G:/mydesign/fir31/fir31.vhd" 188 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.817 ns) + CELL(2.758 ns) 4.575 ns y\[4\] 2 PIN Pin_C17 0 " "Info: 2: + IC(1.817 ns) + CELL(2.758 ns) = 4.575 ns; Loc. = Pin_C17; Fanout = 0; PIN Node = 'y\[4\]'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "4.575 ns" { y[4]~reg0 y[4] } "NODE_NAME" } } } { "G:/mydesign/fir31/fir31.vhd" "" "" { Text "G:/mydesign/fir31/fir31.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.758 ns 60.28 % " "Info: Total cell delay = 2.758 ns ( 60.28 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.817 ns 39.72 % " "Info: Total interconnect delay = 1.817 ns ( 39.72 % )" {  } {  } 0}  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "4.575 ns" { y[4]~reg0 y[4] } "NODE_NAME" } } }  } 0}  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.984 ns" { clk_out y[4]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "4.575 ns" { y[4]~reg0 y[4] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "dff1:g1_0_dffx\|qout\[1\]~reg0 xin\[1\] clk_out -2.135 ns register " "Info: th for register dff1:g1_0_dffx\|qout\[1\]~reg0 (data pin = xin\[1\], clock pin = clk_out) is -2.135 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_out destination 3.007 ns + Longest register " "Info: + Longest clock path from clock clk_out to destination register is 3.007 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.771 ns) 0.771 ns clk_out 1 CLK Pin_M26 256 " "Info: 1: + IC(0.000 ns) + CELL(0.771 ns) = 0.771 ns; Loc. = Pin_M26; Fanout = 256; CLK Node = 'clk_out'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "" { clk_out } "NODE_NAME" } } } { "G:/mydesign/fir31/fir31.vhd" "" "" { Text "G:/mydesign/fir31/fir31.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.676 ns) + CELL(0.560 ns) 3.007 ns dff1:g1_0_dffx\|qout\[1\]~reg0 2 REG LC_X33_Y25_N2 4 " "Info: 2: + IC(1.676 ns) + CELL(0.560 ns) = 3.007 ns; Loc. = LC_X33_Y25_N2; Fanout = 4; REG Node = 'dff1:g1_0_dffx\|qout\[1\]~reg0'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.236 ns" { clk_out dff1:g1_0_dffx|qout[1]~reg0 } "NODE_NAME" } } } { "G:/mydesign/fir31/dff1/dff1.vhd" "" "" { Text "G:/mydesign/fir31/dff1/dff1.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.331 ns 44.26 % " "Info: Total cell delay = 1.331 ns ( 44.26 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.676 ns 55.74 % " "Info: Total interconnect delay = 1.676 ns ( 55.74 % )" {  } {  } 0}  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "3.007 ns" { clk_out dff1:g1_0_dffx|qout[1]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "G:/mydesign/fir31/dff1/dff1.vhd" "" "" { Text "G:/mydesign/fir31/dff1/dff1.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.242 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.242 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.976 ns) 0.976 ns xin\[1\] 1 PIN Pin_C16 4 " "Info: 1: + IC(0.000 ns) + CELL(0.976 ns) = 0.976 ns; Loc. = Pin_C16; Fanout = 4; PIN Node = 'xin\[1\]'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "" { xin[1] } "NODE_NAME" } } } { "G:/mydesign/fir31/fir31.vhd" "" "" { Text "G:/mydesign/fir31/fir31.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.176 ns) + CELL(0.090 ns) 5.242 ns dff1:g1_0_dffx\|qout\[1\]~reg0 2 REG LC_X33_Y25_N2 4 " "Info: 2: + IC(4.176 ns) + CELL(0.090 ns) = 5.242 ns; Loc. = LC_X33_Y25_N2; Fanout = 4; REG Node = 'dff1:g1_0_dffx\|qout\[1\]~reg0'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "4.266 ns" { xin[1] dff1:g1_0_dffx|qout[1]~reg0 } "NODE_NAME" } } } { "G:/mydesign/fir31/dff1/dff1.vhd" "" "" { Text "G:/mydesign/fir31/dff1/dff1.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.066 ns 20.34 % " "Info: Total cell delay = 1.066 ns ( 20.34 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.176 ns 79.66 % " "Info: Total interconnect delay = 4.176 ns ( 79.66 % )" {  } {  } 0}  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "5.242 ns" { xin[1] dff1:g1_0_dffx|qout[1]~reg0 } "NODE_NAME" } } }  } 0}  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "3.007 ns" { clk_out dff1:g1_0_dffx|qout[1]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "5.242 ns" { xin[1] dff1:g1_0_dffx|qout[1]~reg0 } "NODE_NAME" } } }  } 0}