📄 fir31.tan.qmsg
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{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clk_out " "Info: Assuming node clk_out is an undefined clock" { } { { "G:/mydesign/fir31/fir31.vhd" "" "" { Text "G:/mydesign/fir31/fir31.vhd" 8 -1 0 } } { "g:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_out" } } } } } 0} { "Info" "ITDB_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" { } { { "G:/mydesign/fir31/fir31.vhd" "" "" { Text "G:/mydesign/fir31/fir31.vhd" 8 -1 0 } } { "g:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk_out register register dff1:g1_27_dffx\|qout\[1\]~reg0 dff1:g1_28_dffx\|qout\[1\]~reg0 422.12 MHz Internal " "Info: Clock clk_out Internal fmax is restricted to 422.12 MHz between source register dff1:g1_27_dffx\|qout\[1\]~reg0 and destination register dff1:g1_28_dffx\|qout\[1\]~reg0" { { "Info" "ITDB_CLOCK_RATE" "clock 2.369 ns " "Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.654 ns + Longest register register " "Info: + Longest register to register delay is 0.654 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dff1:g1_27_dffx\|qout\[1\]~reg0 1 REG LC_X34_Y23_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y23_N9; Fanout = 1; REG Node = 'dff1:g1_27_dffx\|qout\[1\]~reg0'" { } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "" { dff1:g1_27_dffx|qout[1]~reg0 } "NODE_NAME" } } } { "G:/mydesign/fir31/dff1/dff1.vhd" "" "" { Text "G:/mydesign/fir31/dff1/dff1.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.419 ns) + CELL(0.235 ns) 0.654 ns dff1:g1_28_dffx\|qout\[1\]~reg0 2 REG LC_X34_Y23_N6 4 " "Info: 2: + IC(0.419 ns) + CELL(0.235 ns) = 0.654 ns; Loc. = LC_X34_Y23_N6; Fanout = 4; REG Node = 'dff1:g1_28_dffx\|qout\[1\]~reg0'" { } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "0.654 ns" { dff1:g1_27_dffx|qout[1]~reg0 dff1:g1_28_dffx|qout[1]~reg0 } "NODE_NAME" } } } { "G:/mydesign/fir31/dff1/dff1.vhd" "" "" { Text "G:/mydesign/fir31/dff1/dff1.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.235 ns 35.93 % " "Info: Total cell delay = 0.235 ns ( 35.93 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.419 ns 64.07 % " "Info: Total interconnect delay = 0.419 ns ( 64.07 % )" { } { } 0} } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "0.654 ns" { dff1:g1_27_dffx|qout[1]~reg0 dff1:g1_28_dffx|qout[1]~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_out destination 2.989 ns + Shortest register " "Info: + Shortest clock path from clock clk_out to destination register is 2.989 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.771 ns) 0.771 ns clk_out 1 CLK Pin_M26 256 " "Info: 1: + IC(0.000 ns) + CELL(0.771 ns) = 0.771 ns; Loc. = Pin_M26; Fanout = 256; CLK Node = 'clk_out'" { } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "" { clk_out } "NODE_NAME" } } } { "G:/mydesign/fir31/fir31.vhd" "" "" { Text "G:/mydesign/fir31/fir31.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.658 ns) + CELL(0.560 ns) 2.989 ns dff1:g1_28_dffx\|qout\[1\]~reg0 2 REG LC_X34_Y23_N6 4 " "Info: 2: + IC(1.658 ns) + CELL(0.560 ns) = 2.989 ns; Loc. = LC_X34_Y23_N6; Fanout = 4; REG Node = 'dff1:g1_28_dffx\|qout\[1\]~reg0'" { } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.218 ns" { clk_out dff1:g1_28_dffx|qout[1]~reg0 } "NODE_NAME" } } } { "G:/mydesign/fir31/dff1/dff1.vhd" "" "" { Text "G:/mydesign/fir31/dff1/dff1.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.331 ns 44.53 % " "Info: Total cell delay = 1.331 ns ( 44.53 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.658 ns 55.47 % " "Info: Total interconnect delay = 1.658 ns ( 55.47 % )" { } { } 0} } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.989 ns" { clk_out dff1:g1_28_dffx|qout[1]~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_out source 2.989 ns - Longest register " "Info: - Longest clock path from clock clk_out to source register is 2.989 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.771 ns) 0.771 ns clk_out 1 CLK Pin_M26 256 " "Info: 1: + IC(0.000 ns) + CELL(0.771 ns) = 0.771 ns; Loc. = Pin_M26; Fanout = 256; CLK Node = 'clk_out'" { } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "" { clk_out } "NODE_NAME" } } } { "G:/mydesign/fir31/fir31.vhd" "" "" { Text "G:/mydesign/fir31/fir31.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.658 ns) + CELL(0.560 ns) 2.989 ns dff1:g1_27_dffx\|qout\[1\]~reg0 2 REG LC_X34_Y23_N9 1 " "Info: 2: + IC(1.658 ns) + CELL(0.560 ns) = 2.989 ns; Loc. = LC_X34_Y23_N9; Fanout = 1; REG Node = 'dff1:g1_27_dffx\|qout\[1\]~reg0'" { } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.218 ns" { clk_out dff1:g1_27_dffx|qout[1]~reg0 } "NODE_NAME" } } } { "G:/mydesign/fir31/dff1/dff1.vhd" "" "" { Text "G:/mydesign/fir31/dff1/dff1.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.331 ns 44.53 % " "Info: Total cell delay = 1.331 ns ( 44.53 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.658 ns 55.47 % " "Info: Total interconnect delay = 1.658 ns ( 55.47 % )" { } { } 0} } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.989 ns" { clk_out dff1:g1_27_dffx|qout[1]~reg0 } "NODE_NAME" } } } } 0} } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.989 ns" { clk_out dff1:g1_28_dffx|qout[1]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.989 ns" { clk_out dff1:g1_27_dffx|qout[1]~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" { } { { "G:/mydesign/fir31/dff1/dff1.vhd" "" "" { Text "G:/mydesign/fir31/dff1/dff1.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "G:/mydesign/fir31/dff1/dff1.vhd" "" "" { Text "G:/mydesign/fir31/dff1/dff1.vhd" 12 -1 0 } } } 0} } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "0.654 ns" { dff1:g1_27_dffx|qout[1]~reg0 dff1:g1_28_dffx|qout[1]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.989 ns" { clk_out dff1:g1_28_dffx|qout[1]~reg0 } "NODE_NAME" } } } { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.989 ns" { clk_out dff1:g1_27_dffx|qout[1]~reg0 } "NODE_NAME" } } } } 0} } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "" { dff1:g1_28_dffx|qout[1]~reg0 } "NODE_NAME" } } } { "G:/mydesign/fir31/dff1/dff1.vhd" "" "" { Text "G:/mydesign/fir31/dff1/dff1.vhd" 12 -1 0 } } } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register mul:u12\|states_t\[6\] register mul:u12\|states_p\[11\] 239.18 MHz 4.181 ns Internal " "Info: Clock clk has Internal fmax of 239.18 MHz between source register mul:u12\|states_t\[6\] and destination register mul:u12\|states_p\[11\] (period= 4.181 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.003 ns + Longest register register " "Info: + Longest register to register delay is 4.003 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mul:u12\|states_t\[6\] 1 REG LC_X33_Y13_N5 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X33_Y13_N5; Fanout = 5; REG Node = 'mul:u12\|states_t\[6\]'" { } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "" { mul:u12|states_t[6] } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.984 ns) + CELL(0.533 ns) 1.517 ns mul:u12\|i~565COUT 2 COMB LC_X35_Y13_N9 6 " "Info: 2: + IC(0.984 ns) + CELL(0.533 ns) = 1.517 ns; Loc. = LC_X35_Y13_N9; Fanout = 6; COMB Node = 'mul:u12\|i~565COUT'" { } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "1.517 ns" { mul:u12|states_t[6] mul:u12|i~565COUT } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.493 ns) 2.010 ns mul:u12\|i~570 3 COMB LC_X35_Y12_N4 1 " "Info: 3: + IC(0.000 ns) + CELL(0.493 ns) = 2.010 ns; Loc. = LC_X35_Y12_N4; Fanout = 1; COMB Node = 'mul:u12\|i~570'" { } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "0.493 ns" { mul:u12|i~565COUT mul:u12|i~570 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.590 ns) + CELL(0.087 ns) 2.687 ns mul:u12\|i~3578 4 COMB LC_X36_Y12_N9 1 " "Info: 4: + IC(0.590 ns) + CELL(0.087 ns) = 2.687 ns; Loc. = LC_X36_Y12_N9; Fanout = 1; COMB Node = 'mul:u12\|i~3578'" { } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "0.677 ns" { mul:u12|i~570 mul:u12|i~3578 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.081 ns) + CELL(0.235 ns) 4.003 ns mul:u12\|states_p\[11\] 5 REG LC_X35_Y14_N8 4 " "Info: 5: + IC(1.081 ns) + CELL(0.235 ns) = 4.003 ns; Loc. = LC_X35_Y14_N8; Fanout = 4; REG Node = 'mul:u12\|states_p\[11\]'" { } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "1.316 ns" { mul:u12|i~3578 mul:u12|states_p[11] } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.348 ns 33.67 % " "Info: Total cell delay = 1.348 ns ( 33.67 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.655 ns 66.33 % " "Info: Total interconnect delay = 2.655 ns ( 66.33 % )" { } { } 0} } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "4.003 ns" { mul:u12|states_t[6] mul:u12|i~565COUT mul:u12|i~570 mul:u12|i~3578 mul:u12|states_p[11] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.008 ns - Smallest " "Info: - Smallest clock skew is 0.008 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.984 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 2.984 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clk 1 CLK Pin_M24 780 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 780; CLK Node = 'clk'" { } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "G:/mydesign/fir31/fir31.vhd" "" "" { Text "G:/mydesign/fir31/fir31.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.762 ns) + CELL(0.560 ns) 2.984 ns mul:u12\|states_p\[11\] 2 REG LC_X35_Y14_N8 4 " "Info: 2: + IC(1.762 ns) + CELL(0.560 ns) = 2.984 ns; Loc. = LC_X35_Y14_N8; Fanout = 4; REG Node = 'mul:u12\|states_p\[11\]'" { } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.322 ns" { clk mul:u12|states_p[11] } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns 40.95 % " "Info: Total cell delay = 1.222 ns ( 40.95 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.762 ns 59.05 % " "Info: Total interconnect delay = 1.762 ns ( 59.05 % )" { } { } 0} } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.984 ns" { clk mul:u12|states_p[11] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.976 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 2.976 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clk 1 CLK Pin_M24 780 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 780; CLK Node = 'clk'" { } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "G:/mydesign/fir31/fir31.vhd" "" "" { Text "G:/mydesign/fir31/fir31.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.754 ns) + CELL(0.560 ns) 2.976 ns mul:u12\|states_t\[6\] 2 REG LC_X33_Y13_N5 5 " "Info: 2: + IC(1.754 ns) + CELL(0.560 ns) = 2.976 ns; Loc. = LC_X33_Y13_N5; Fanout = 5; REG Node = 'mul:u12\|states_t\[6\]'" { } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.314 ns" { clk mul:u12|states_t[6] } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns 41.06 % " "Info: Total cell delay = 1.222 ns ( 41.06 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.754 ns 58.94 % " "Info: Total interconnect delay = 1.754 ns ( 58.94 % )" { } { } 0} } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.976 ns" { clk mul:u12|states_t[6] } "NODE_NAME" } } } } 0} } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.984 ns" { clk mul:u12|states_p[11] } "NODE_NAME" } } } { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.976 ns" { clk mul:u12|states_t[6] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" { } { { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } } } 0} } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "4.003 ns" { mul:u12|states_t[6] mul:u12|i~565COUT mul:u12|i~570 mul:u12|i~3578 mul:u12|states_p[11] } "NODE_NAME" } } } { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.984 ns" { clk mul:u12|states_p[11] } "NODE_NAME" } } } { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "2.976 ns" { clk mul:u12|states_t[6] } "NODE_NAME" } } } } 0}
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