mux_7ac.tdf

设计一个线性相位FIR滤波器（31阶） 输入8位

--lpm_mux CASCADE_CHAIN=IGNORE DEVICE_FAMILY=Stratix IGNORE_CASCADE_BUFFERS=OFF LPM_SIZE=8 LPM_WIDTH=1 LPM_WIDTHS=3 data result sel
--VERSION_BEGIN 4.0 cbx_lpm_mux 2003:10:21:14:09:22:SJ cbx_mgl 2004:01:13:14:00:54:SJ  VERSION_END


--  Copyright (C) 1988-2004 Altera Corporation
--  Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
--  support information,  device programming or simulation file,  and any other
--  associated  documentation or information  provided by  Altera  or a partner
--  under  Altera's   Megafunction   Partnership   Program  may  be  used  only
--  to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
--  other  use  of such  megafunction  design,  netlist,  support  information,
--  device programming or simulation file,  or any other  related documentation
--  or information  is prohibited  for  any  other purpose,  including, but not
--  limited to  modification,  reverse engineering,  de-compiling, or use  with
--  any other  silicon devices,  unless such use is  explicitly  licensed under
--  a separate agreement with  Altera  or a megafunction partner.  Title to the
--  intellectual property,  including patents,  copyrights,  trademarks,  trade
--  secrets,  or maskworks,  embodied in any such megafunction design, netlist,
--  support  information,  device programming or simulation file,  or any other
--  related documentation or information provided by  Altera  or a megafunction
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--  licensors. No other licenses, including any licenses needed under any third
--  party's intellectual property, are provided herein.



--synthesis_resources = lut 5 
SUBDESIGN mux_7ac
( 
	data[7..0]	:	input;
	result[0..0]	:	output;
	sel[2..0]	:	input;
) 
VARIABLE 
	result_node[0..0]	: WIRE;
	sel_ffs_wire[2..0]	: WIRE;
	sel_node[2..0]	: WIRE;
	w_data38w[3..0]	: WIRE;
	w_data39w[3..0]	: WIRE;
	w_data9w[7..0]	: WIRE;
	w_result10w	: WIRE;
	w_result35w	: WIRE;
	w_result36w	: WIRE;
	w_result37w	: WIRE;
	w_result43w	: WIRE;
	w_result44w	: WIRE;
	w_result64w	: WIRE;
	w_result65w	: WIRE;
	w_sel40w[1..0]	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( w_result10w);
	sel_ffs_wire[] = ( sel[2..0]);
	sel_node[] = ( sel_ffs_wire[2..2], sel[1..0]);
	w_data38w[3..0] = w_data9w[3..0];
	w_data39w[3..0] = w_data9w[7..4];
	w_data9w[] = ( data[7..0]);
	w_result10w = w_result35w;
	w_result35w = ((sel_node[2..2] & w_result37w) # ((! sel_node[2..2]) & w_result36w));
	w_result36w = w_result43w;
	w_result37w = w_result64w;
	w_result43w = (((w_data38w[1..1] & w_sel40w[0..0]) & (! w_result44w)) # (w_result44w & (w_data38w[3..3] # (! w_sel40w[0..0]))));
	w_result44w = (((w_data38w[0..0] & (! w_sel40w[1..1])) & (! w_sel40w[0..0])) # (w_sel40w[1..1] & (w_sel40w[0..0] # w_data38w[2..2])));
	w_result64w = (((w_data39w[1..1] & w_sel40w[0..0]) & (! w_result65w)) # (w_result65w & (w_data39w[3..3] # (! w_sel40w[0..0]))));
	w_result65w = (((w_data39w[0..0] & (! w_sel40w[1..1])) & (! w_sel40w[0..0])) # (w_sel40w[1..1] & (w_sel40w[0..0] # w_data39w[2..2])));
	w_sel40w[1..0] = sel_node[1..0];
END;
--VALID FILE