fir31.fit.qmsg

设计一个线性相位FIR滤波器（31阶） 输入8位

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.213 ns register register " "Info: Estimated most critical path is register to register delay of 4.213 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mul:u12\|states_t\[6\] 1 REG LAB_X33_Y13 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X33_Y13; Fanout = 5; REG Node = 'mul:u12\|states_t\[6\]'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "" { mul:u12|states_t[6] } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.893 ns) + CELL(0.644 ns) 1.537 ns mul:u12\|i~565COUT 2 COMB LAB_X35_Y13 6 " "Info: 2: + IC(0.893 ns) + CELL(0.644 ns) = 1.537 ns; Loc. = LAB_X35_Y13; Fanout = 6; COMB Node = 'mul:u12\|i~565COUT'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "1.537 ns" { mul:u12|states_t[6] mul:u12|i~565COUT } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.493 ns) 2.030 ns mul:u12\|i~570 3 COMB LAB_X35_Y12 1 " "Info: 3: + IC(0.000 ns) + CELL(0.493 ns) = 2.030 ns; Loc. = LAB_X35_Y12; Fanout = 1; COMB Node = 'mul:u12\|i~570'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "0.493 ns" { mul:u12|i~565COUT mul:u12|i~570 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.314 ns) + CELL(0.459 ns) 2.803 ns mul:u12\|i~3578 4 COMB LAB_X36_Y12 1 " "Info: 4: + IC(0.314 ns) + CELL(0.459 ns) = 2.803 ns; Loc. = LAB_X36_Y12; Fanout = 1; COMB Node = 'mul:u12\|i~3578'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "0.773 ns" { mul:u12|i~570 mul:u12|i~3578 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.827 ns) + CELL(0.583 ns) 4.213 ns mul:u12\|states_p\[11\] 5 REG LAB_X35_Y14 4 " "Info: 5: + IC(0.827 ns) + CELL(0.583 ns) = 4.213 ns; Loc. = LAB_X35_Y14; Fanout = 4; REG Node = 'mul:u12\|states_p\[11\]'" {  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "1.410 ns" { mul:u12|i~3578 mul:u12|states_p[11] } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.179 ns 51.72 % " "Info: Total cell delay = 2.179 ns ( 51.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.034 ns 48.28 % " "Info: Total interconnect delay = 2.034 ns ( 48.28 % )" {  } {  } 0}  } { { "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31_cmp.qrpt" Compiler "fir31" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/mydesign/fir31/db/fir31.quartus_db" { Floorplan "" "" "4.213 ns" { mul:u12|states_t[6] mul:u12|i~565COUT mul:u12|i~570 mul:u12|i~3578 mul:u12|states_p[11] } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "2 " "Info: Estimated interconnect usage is 2% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "105 " "Info: Fitter placement operations ending: elapsed time = 105 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "21 " "Info: Fitter routing operations ending: elapsed time = 21 seconds" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 21 20:17:31 2005 " "Info: Processing ended: Wed Dec 21 20:17:31 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:04:26 " "Info: Elapsed time: 00:04:26" {  } {  } 0}  } {  } 0}