📄 fir31.map.rpt
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Analysis & Synthesis report for fir31
Mon Dec 26 14:54:51 2005
Version 4.0 Build 190 1/28/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Default Parameter Settings
5. Analysis & Synthesis Files Read
6. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+---------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+---------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Dec 26 14:54:51 2005 ;
; Revision Name ; fir31 ;
; Top-level Entity Name ; fir31 ;
; Family ; Stratix ;
+-----------------------------+---------------------------------------+
+----------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+-----------------------------------------------------------------------------------------
; Option ; Setting ; Default Value ;
+---------------------------------------------------------+--------------+---------------+
; Top-level entity name ; fir31 ; ;
; Auto Resource Sharing ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Perform gate-level register retiming ; Off ; Off ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Remove Duplicate Logic ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Auto Carry Chains ; On ; On ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II ; 70 ; 70 ;
; Optimization Technique -- Stratix/Stratix GX ; Balanced ; Balanced ;
; Auto Global Register Control Signals ; On ; On ;
; Auto Global Clock ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore CARRY Buffers ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Power-Up Don't Care ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; State Machine Processing ; Auto ; Auto ;
; Family name ; Stratix ; Stratix ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; Preserve fewer node names ; On ; On ;
; Disk space/compilation speed tradeoff ; Normal ; Normal ;
; Create Debugging Nodes for IP Cores ; off ; off ;
+---------------------------------------------------------+--------------+---------------+
+-------------------------------------------------+
; Analysis & Synthesis Default Parameter Settings ;
+--------------------------------------------------
; Name ; Setting ;
+--------------------+----------------------------+
; CARRY_CHAIN ; MANUAL ;
; CASCADE_CHAIN ; MANUAL ;
; OPTIMIZE_FOR_SPEED ; 5 ;
; STYLE ; FAST ;
+--------------------+----------------------------+
+-----------------------------------------------------------+
; Analysis & Synthesis Files Read ;
+------------------------------------------------------------
; File Name ; Read ;
+----------------------------------------------------+------+
; mul/mul.vhd ; Read ;
; dff1/dff1.vhd ; Read ;
; F:/mydesign/fir31/fir31.vhd ; Read ;
; f:/quartus/libraries/megafunctions/lpm_add_sub.tdf ; Read ;
; f:/quartus/libraries/megafunctions/addcore.tdf ; Read ;
; f:/quartus/libraries/megafunctions/a_csnbuffer.tdf ; Read ;
; f:/quartus/libraries/megafunctions/altshift.tdf ; Read ;
; f:/quartus/libraries/megafunctions/lpm_mux.tdf ; Read ;
; F:/mydesign/fir31/db/mux_7ac.tdf ; Read ;
+----------------------------------------------------+------+
+--------------------------------+
; Analysis & Synthesis Messages ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
Info: Processing started: Mon Dec 26 14:54:40 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off fir31 -c fir31 --generate_functional_sim_netlist
Info: Found 3 design units and 1 entities in source file mul/mul.vhd
Info: Found design unit 1: nine_bit_int
Info: Found design unit 2: mul-a
Info: Found entity 1: mul
Info: Found 2 design units and 1 entities in source file dff1/dff1.vhd
Info: Found design unit 1: dff1-rtl
Info: Found entity 1: dff1
Info: Using design file fir31.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: fir31-rtl
Info: Found entity 1: fir31
Warning: Tied undriven net cxout1[17] at fir31.vhd(59) to GND or VCC
Warning: Tied undriven net cxout1[16] at fir31.vhd(59) to GND or VCC
Warning: Tied undriven net cxout2[17] at fir31.vhd(60) to GND or VCC
Warning: Tied undriven net cxout2[16] at fir31.vhd(60) to GND or VCC
Warning: Tied undriven net cxout3[17] at fir31.vhd(61) to GND or VCC
Warning: Tied undriven net cxout3[16] at fir31.vhd(61) to GND or VCC
Warning: Tied undriven net cxout4[17] at fir31.vhd(62) to GND or VCC
Warning: Tied undriven net cxout4[16] at fir31.vhd(62) to GND or VCC
Warning: Tied undriven net cxout5[17] at fir31.vhd(63) to GND or VCC
Warning: Tied undriven net cxout5[16] at fir31.vhd(63) to GND or VCC
Warning: Tied undriven net cxout6[17] at fir31.vhd(64) to GND or VCC
Warning: Tied undriven net cxout6[16] at fir31.vhd(64) to GND or VCC
Warning: Tied undriven net cxout7[17] at fir31.vhd(65) to GND or VCC
Warning: Tied undriven net cxout7[16] at fir31.vhd(65) to GND or VCC
Warning: Tied undriven net cxout8[17] at fir31.vhd(66) to GND or VCC
Warning: Tied undriven net cxout8[16] at fir31.vhd(66) to GND or VCC
Warning: Tied undriven net cxout9[17] at fir31.vhd(67) to GND or VCC
Warning: Tied undriven net cxout9[16] at fir31.vhd(67) to GND or VCC
Warning: Tied undriven net cxout10[17] at fir31.vhd(68) to GND or VCC
Warning: Tied undriven net cxout10[16] at fir31.vhd(68) to GND or VCC
Warning: Tied undriven net cxout11[17] at fir31.vhd(69) to GND or VCC
Warning: Tied undriven net cxout11[16] at fir31.vhd(69) to GND or VCC
Warning: Tied undriven net cxout12[17] at fir31.vhd(70) to GND or VCC
Warning: Tied undriven net cxout12[16] at fir31.vhd(70) to GND or VCC
Warning: Tied undriven net cxout13[17] at fir31.vhd(71) to GND or VCC
Warning: Tied undriven net cxout13[16] at fir31.vhd(71) to GND or VCC
Warning: Tied undriven net cxout14[17] at fir31.vhd(72) to GND or VCC
Warning: Tied undriven net cxout14[16] at fir31.vhd(72) to GND or VCC
Warning: Tied undriven net cxout15[17] at fir31.vhd(73) to GND or VCC
Warning: Tied undriven net cxout15[16] at fir31.vhd(73) to GND or VCC
Info: Found 1 design units and 1 entities in source file ../../quartus/libraries/megafunctions/lpm_add_sub.tdf
Info: Found entity 1: lpm_add_sub
Info: Found 1 design units and 1 entities in source file ../../quartus/libraries/megafunctions/addcore.tdf
Info: Found entity 1: addcore
Info: Found 1 design units and 1 entities in source file ../../quartus/libraries/megafunctions/a_csnbuffer.tdf
Info: Found entity 1: a_csnbuffer
Info: Found 1 design units and 1 entities in source file ../../quartus/libraries/megafunctions/altshift.tdf
Info: Found entity 1: altshift
Info: Found 1 design units and 1 entities in source file ../../quartus/libraries/megafunctions/lpm_mux.tdf
Info: Found entity 1: lpm_mux
Info: Found 1 design units and 1 entities in source file db/mux_7ac.tdf
Info: Found entity 1: mux_7ac
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 30 warnings
Info: Processing ended: Mon Dec 26 14:54:50 2005
Info: Elapsed time: 00:00:10
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