mul.vhd

来自「设计一个线性相位FIR滤波器（31阶） 输入8位」· VHDL 代码 · 共 48 行

package nine_bit_int is
subtype byte is integer range -256 to 255;
subtype twobytes is integer range -32768 to 32767;
end nine_bit_int;
library work;
use work.nine_bit_int.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity mul is 
port(clk:in std_logic;
      x:in byte;
      a: in std_logic_vector(7 downto 0);
      y:out twobytes);
 end mul;
architecture a of mul is
type state_type is(s0,s1,s2);
signal state:state_type;
begin
states:process
variable p,t:twobytes;
variable count: integer range 0 to 8;
begin
wait until clk='0';
case state is
 when s0=>
state<=s1;
count:=0;
p:=0;
t:=x;
when s1=>
if count=8 then 
state<=s2;
else
if a(count)='1' then 
p:=p+t;
end if;
t:=t*2;
count:=count+1;
state<=s1;
end if;
when s2=>
y<=p;
state<=s0;
end case;
end process;
end a;