📄 mul.csf.qmsg
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --import_settings_files=off --export_settings_files=off mul -c mul " "Info: Command: quartus_asm --import_settings_files=off --export_settings_files=off mul -c mul" { } { } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 19 22:29:08 2005 " "Info: Processing ended: Mon Dec 19 22:29:08 2005" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" { } { } 0} } { } 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" { } { } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 19 22:29:09 2005 " "Info: Processing started: Mon Dec 19 22:29:09 2005" { } { } 0} } { } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off mul -c mul --timing_analysis_only " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off mul -c mul --timing_analysis_only" { } { } 0}
{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" { } { { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 11 -1 0 } } { "g:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register states_count\[1\] register states_p\[14\] 241.2 MHz 4.146 ns Internal " "Info: Clock clk has Internal fmax of 241.2 MHz between source register states_count\[1\] and destination register states_p\[14\] (period= 4.146 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.947 ns + Longest register register " "Info: + Longest register to register delay is 3.947 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns states_count\[1\] 1 REG LC_X31_Y26_N7 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y26_N7; Fanout = 8; REG Node = 'states_count\[1\]'" { } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "" { states_count[1] } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.474 ns) + CELL(0.213 ns) 0.687 ns i~527 2 COMB LC_X31_Y26_N0 1 " "Info: 2: + IC(0.474 ns) + CELL(0.213 ns) = 0.687 ns; Loc. = LC_X31_Y26_N0; Fanout = 1; COMB Node = 'i~527'" { } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "0.687 ns" { states_count[1] i~527 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.087 ns) 0.913 ns i~528 3 COMB LC_X31_Y26_N1 1 " "Info: 3: + IC(0.139 ns) + CELL(0.087 ns) = 0.913 ns; Loc. = LC_X31_Y26_N1; Fanout = 1; COMB Node = 'i~528'" { } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "0.226 ns" { i~527 i~528 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.364 ns) + CELL(0.213 ns) 1.490 ns i28~111 4 COMB LC_X31_Y26_N4 1 " "Info: 4: + IC(0.364 ns) + CELL(0.213 ns) = 1.490 ns; Loc. = LC_X31_Y26_N4; Fanout = 1; COMB Node = 'i28~111'" { } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "0.577 ns" { i~528 i28~111 } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 32 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.253 ns) + CELL(0.087 ns) 1.830 ns i28~112 5 COMB LC_X31_Y26_N5 15 " "Info: 5: + IC(0.253 ns) + CELL(0.087 ns) = 1.830 ns; Loc. = LC_X31_Y26_N5; Fanout = 15; COMB Node = 'i28~112'" { } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "0.340 ns" { i28~111 i28~112 } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 32 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.416 ns) + CELL(0.213 ns) 3.459 ns i~4896 6 COMB LC_X34_Y24_N4 1 " "Info: 6: + IC(1.416 ns) + CELL(0.213 ns) = 3.459 ns; Loc. = LC_X34_Y24_N4; Fanout = 1; COMB Node = 'i~4896'" { } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "1.629 ns" { i28~112 i~4896 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.253 ns) + CELL(0.235 ns) 3.947 ns states_p\[14\] 7 REG LC_X34_Y24_N5 4 " "Info: 7: + IC(0.253 ns) + CELL(0.235 ns) = 3.947 ns; Loc. = LC_X34_Y24_N5; Fanout = 4; REG Node = 'states_p\[14\]'" { } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "0.488 ns" { i~4896 states_p[14] } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.048 ns 26.55 % " "Info: Total cell delay = 1.048 ns ( 26.55 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.899 ns 73.45 % " "Info: Total interconnect delay = 2.899 ns ( 73.45 % )" { } { } 0} } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "3.947 ns" { states_count[1] i~527 i~528 i28~111 i28~112 i~4896 states_p[14] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.013 ns - Smallest " "Info: - Smallest clock skew is -0.013 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.882 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 2.882 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clk 1 CLK Pin_M24 52 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 52; CLK Node = 'clk'" { } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.660 ns) + CELL(0.560 ns) 2.882 ns states_p\[14\] 2 REG LC_X34_Y24_N5 4 " "Info: 2: + IC(1.660 ns) + CELL(0.560 ns) = 2.882 ns; Loc. = LC_X34_Y24_N5; Fanout = 4; REG Node = 'states_p\[14\]'" { } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "2.220 ns" { clk states_p[14] } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns 42.40 % " "Info: Total cell delay = 1.222 ns ( 42.40 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.660 ns 57.60 % " "Info: Total interconnect delay = 1.660 ns ( 57.60 % )" { } { } 0} } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "2.882 ns" { clk states_p[14] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.895 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 2.895 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clk 1 CLK Pin_M24 52 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 52; CLK Node = 'clk'" { } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.673 ns) + CELL(0.560 ns) 2.895 ns states_count\[1\] 2 REG LC_X31_Y26_N7 8 " "Info: 2: + IC(1.673 ns) + CELL(0.560 ns) = 2.895 ns; Loc. = LC_X31_Y26_N7; Fanout = 8; REG Node = 'states_count\[1\]'" { } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "2.233 ns" { clk states_count[1] } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns 42.21 % " "Info: Total cell delay = 1.222 ns ( 42.21 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.673 ns 57.79 % " "Info: Total interconnect delay = 1.673 ns ( 57.79 % )" { } { } 0} } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "2.895 ns" { clk states_count[1] } "NODE_NAME" } } } } 0} } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "2.882 ns" { clk states_p[14] } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "2.895 ns" { clk states_count[1] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" { } { { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } } } 0} } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "3.947 ns" { states_count[1] i~527 i~528 i28~111 i28~112 i~4896 states_p[14] } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "2.882 ns" { clk states_p[14] } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "2.895 ns" { clk states_count[1] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "states_p\[14\] a\[2\] clk 6.302 ns register " "Info: tsu for register states_p\[14\] (data pin = a\[2\], clock pin = clk) is 6.302 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.174 ns + Longest pin register " "Info: + Longest pin to register delay is 9.174 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.905 ns) 0.905 ns a\[2\] 1 PIN Pin_D12 1 " "Info: 1: + IC(0.000 ns) + CELL(0.905 ns) = 0.905 ns; Loc. = Pin_D12; Fanout = 1; PIN Node = 'a\[2\]'" { } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "" { a[2] } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 13 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.776 ns) + CELL(0.459 ns) 6.140 ns i~528 2 COMB LC_X31_Y26_N1 1 " "Info: 2: + IC(4.776 ns) + CELL(0.459 ns) = 6.140 ns; Loc. = LC_X31_Y26_N1; Fanout = 1; COMB Node = 'i~528'" { } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "5.235 ns" { a[2] i~528 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.364 ns) + CELL(0.213 ns) 6.717 ns i28~111 3 COMB LC_X31_Y26_N4 1 " "Info: 3: + IC(0.364 ns) + CELL(0.213 ns) = 6.717 ns; Loc. = LC_X31_Y26_N4; Fanout = 1; COMB Node = 'i28~111'" { } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "0.577 ns" { i~528 i28~111 } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 32 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.253 ns) + CELL(0.087 ns) 7.057 ns i28~112 4 COMB LC_X31_Y26_N5 15 " "Info: 4: + IC(0.253 ns) + CELL(0.087 ns) = 7.057 ns; Loc. = LC_X31_Y26_N5; Fanout = 15; COMB Node = 'i28~112'" { } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "0.340 ns" { i28~111 i28~112 } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 32 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.416 ns) + CELL(0.213 ns) 8.686 ns i~4896 5 COMB LC_X34_Y24_N4 1 " "Info: 5: + IC(1.416 ns) + CELL(0.213 ns) = 8.686 ns; Loc. = LC_X34_Y24_N4; Fanout = 1; COMB Node = 'i~4896'" { } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "1.629 ns" { i28~112 i~4896 } "NODE_NAME" } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.253 ns) + CELL(0.235 ns) 9.174 ns states_p\[14\] 6 REG LC_X34_Y24_N5 4 " "Info: 6: + IC(0.253 ns) + CELL(0.235 ns) = 9.174 ns; Loc. = LC_X34_Y24_N5; Fanout = 4; REG Node = 'states_p\[14\]'" { } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "0.488 ns" { i~4896 states_p[14] } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.112 ns 23.02 % " "Info: Total cell delay = 2.112 ns ( 23.02 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.062 ns 76.98 % " "Info: Total interconnect delay = 7.062 ns ( 76.98 % )" { } { } 0} } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "9.174 ns" { a[2] i~528 i28~111 i28~112 i~4896 states_p[14] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.882 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 2.882 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clk 1 CLK Pin_M24 52 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 52; CLK Node = 'clk'" { } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.660 ns) + CELL(0.560 ns) 2.882 ns states_p\[14\] 2 REG LC_X34_Y24_N5 4 " "Info: 2: + IC(1.660 ns) + CELL(0.560 ns) = 2.882 ns; Loc. = LC_X34_Y24_N5; Fanout = 4; REG Node = 'states_p\[14\]'" { } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "2.220 ns" { clk states_p[14] } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns 42.40 % " "Info: Total cell delay = 1.222 ns ( 42.40 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.660 ns 57.60 % " "Info: Total interconnect delay = 1.660 ns ( 57.60 % )" { } { } 0} } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "2.882 ns" { clk states_p[14] } "NODE_NAME" } } } } 0} } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "9.174 ns" { a[2] i~528 i28~111 i28~112 i~4896 states_p[14] } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "2.882 ns" { clk states_p[14] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk y\[14\] y\[14\]~reg0 7.813 ns register " "Info: tco from clock clk to destination pin y\[14\] through register y\[14\]~reg0 is 7.813 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.899 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 2.899 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clk 1 CLK Pin_M24 52 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 52; CLK Node = 'clk'" { } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.677 ns) + CELL(0.560 ns) 2.899 ns y\[14\]~reg0 2 REG LC_X34_Y27_N2 1 " "Info: 2: + IC(1.677 ns) + CELL(0.560 ns) = 2.899 ns; Loc. = LC_X34_Y27_N2; Fanout = 1; REG Node = 'y\[14\]~reg0'" { } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "2.237 ns" { clk y[14]~reg0 } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns 42.15 % " "Info: Total cell delay = 1.222 ns ( 42.15 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.677 ns 57.85 % " "Info: Total interconnect delay = 1.677 ns ( 57.85 % )" { } { } 0} } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "2.899 ns" { clk y[14]~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" { } { { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.738 ns + Longest register pin " "Info: + Longest register to pin delay is 4.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns y\[14\]~reg0 1 REG LC_X34_Y27_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X34_Y27_N2; Fanout = 1; REG Node = 'y\[14\]~reg0'" { } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "" { y[14]~reg0 } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.980 ns) + CELL(2.758 ns) 4.738 ns y\[14\] 2 PIN Pin_A19 0 " "Info: 2: + IC(1.980 ns) + CELL(2.758 ns) = 4.738 ns; Loc. = Pin_A19; Fanout = 0; PIN Node = 'y\[14\]'" { } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "4.738 ns" { y[14]~reg0 y[14] } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.758 ns 58.21 % " "Info: Total cell delay = 2.758 ns ( 58.21 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.980 ns 41.79 % " "Info: Total interconnect delay = 1.980 ns ( 41.79 % )" { } { } 0} } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "4.738 ns" { y[14]~reg0 y[14] } "NODE_NAME" } } } } 0} } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "2.899 ns" { clk y[14]~reg0 } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "4.738 ns" { y⌨️ 快捷键说明
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