mul.fit.qmsg

设计一个线性相位FIR滤波器（31阶） 输入8位

{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.564 ns register register " "Info: Estimated most critical path is register to register delay of 4.564 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns states_count\[0\] 1 REG LAB_X31_Y26 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X31_Y26; Fanout = 8; REG Node = 'states_count\[0\]'" {  } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "" { states_count[0] } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.120 ns) + CELL(0.459 ns) 0.579 ns i~529 2 COMB LAB_X31_Y26 1 " "Info: 2: + IC(0.120 ns) + CELL(0.459 ns) = 0.579 ns; Loc. = LAB_X31_Y26; Fanout = 1; COMB Node = 'i~529'" {  } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "0.579 ns" { states_count[0] i~529 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.366 ns) + CELL(0.213 ns) 1.158 ns i~530 3 COMB LAB_X31_Y26 1 " "Info: 3: + IC(0.366 ns) + CELL(0.213 ns) = 1.158 ns; Loc. = LAB_X31_Y26; Fanout = 1; COMB Node = 'i~530'" {  } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "0.579 ns" { i~529 i~530 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.120 ns) + CELL(0.459 ns) 1.737 ns i28~111 4 COMB LAB_X31_Y26 1 " "Info: 4: + IC(0.120 ns) + CELL(0.459 ns) = 1.737 ns; Loc. = LAB_X31_Y26; Fanout = 1; COMB Node = 'i28~111'" {  } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "0.579 ns" { i~530 i28~111 } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.120 ns) + CELL(0.459 ns) 2.316 ns i28~112 5 COMB LAB_X31_Y26 15 " "Info: 5: + IC(0.120 ns) + CELL(0.459 ns) = 2.316 ns; Loc. = LAB_X31_Y26; Fanout = 15; COMB Node = 'i28~112'" {  } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "0.579 ns" { i28~111 i28~112 } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.458 ns) + CELL(0.087 ns) 3.861 ns i~4896 6 COMB LAB_X34_Y24 1 " "Info: 6: + IC(1.458 ns) + CELL(0.087 ns) = 3.861 ns; Loc. = LAB_X34_Y24; Fanout = 1; COMB Node = 'i~4896'" {  } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "1.545 ns" { i28~112 i~4896 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.120 ns) + CELL(0.583 ns) 4.564 ns states_p\[14\] 7 REG LAB_X34_Y24 4 " "Info: 7: + IC(0.120 ns) + CELL(0.583 ns) = 4.564 ns; Loc. = LAB_X34_Y24; Fanout = 4; REG Node = 'states_p\[14\]'" {  } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "0.703 ns" { i~4896 states_p[14] } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.260 ns 49.52 % " "Info: Total cell delay = 2.260 ns ( 49.52 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.304 ns 50.48 % " "Info: Total interconnect delay = 2.304 ns ( 50.48 % )" {  } {  } 0}  } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "4.564 ns" { states_count[0] i~529 i~530 i28~111 i28~112 i~4896 states_p[14] } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_PLACER_ESTIMATED_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Estimated interconnect usage is 1% of the available device resources" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "3 " "Info: Fitter placement operations ending: elapsed time = 3 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "1 " "Info: Fitter routing operations ending: elapsed time = 1 seconds" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 19 22:29:02 2005 " "Info: Processing ended: Mon Dec 19 22:29:02 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:35 " "Info: Elapsed time: 00:00:35" {  } {  } 0}  } {  } 0}