mul.tan.qmsg

设计一个线性相位FIR滤波器（31阶） 输入8位

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk y\[3\] y\[3\]~reg0 7.170 ns register " "Info: Minimum tco from clock clk to destination pin y\[3\] through register y\[3\]~reg0 is 7.170 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.899 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 2.899 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clk 1 CLK Pin_M24 52 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 52; CLK Node = 'clk'" {  } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.677 ns) + CELL(0.560 ns) 2.899 ns y\[3\]~reg0 2 REG LC_X33_Y27_N6 1 " "Info: 2: + IC(1.677 ns) + CELL(0.560 ns) = 2.899 ns; Loc. = LC_X33_Y27_N6; Fanout = 1; REG Node = 'y\[3\]~reg0'" {  } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "2.237 ns" { clk y[3]~reg0 } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns 42.15 % " "Info: Total cell delay = 1.222 ns ( 42.15 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.677 ns 57.85 % " "Info: Total interconnect delay = 1.677 ns ( 57.85 % )" {  } {  } 0}  } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "2.899 ns" { clk y[3]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.095 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.095 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns y\[3\]~reg0 1 REG LC_X33_Y27_N6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X33_Y27_N6; Fanout = 1; REG Node = 'y\[3\]~reg0'" {  } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "" { y[3]~reg0 } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.337 ns) + CELL(2.758 ns) 4.095 ns y\[3\] 2 PIN Pin_C15 0 " "Info: 2: + IC(1.337 ns) + CELL(2.758 ns) = 4.095 ns; Loc. = Pin_C15; Fanout = 0; PIN Node = 'y\[3\]'" {  } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "4.095 ns" { y[3]~reg0 y[3] } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/mul.vhd" "" "" { Text "G:/mydesign/fir31/mul/mul.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.758 ns 67.35 % " "Info: Total cell delay = 2.758 ns ( 67.35 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.337 ns 32.65 % " "Info: Total interconnect delay = 1.337 ns ( 32.65 % )" {  } {  } 0}  } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "4.095 ns" { y[3]~reg0 y[3] } "NODE_NAME" } } }  } 0}  } { { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "2.899 ns" { clk y[3]~reg0 } "NODE_NAME" } } } { "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" "" "" { Report "G:/mydesign/fir31/mul/db/mul_cmp.qrpt" Compiler "mul" "UNKNOWN" "V1" "G:/mydesign/fir31/mul/db/mul.quartus_db" { Floorplan "" "" "4.095 ns" { y[3]~reg0 y[3] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 19 22:29:10 2005 " "Info: Processing ended: Mon Dec 19 22:29:10 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}