📄 shift_taps_2ed.tdf
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--altshift_taps DEVICE_FAMILY=Stratix NUMBER_OF_TAPS=1 TAP_DISTANCE=3 WIDTH=14 clken clock shiftin taps CARRY_CHAIN=MANUAL CARRY_CHAIN_LENGTH=70
--VERSION_BEGIN 4.0 cbx_altdpram 2003:08:18:15:59:18:SJ cbx_altshift_taps 2003:08:19:18:09:06:SJ cbx_altsyncram 2003:12:02:15:28:30:SJ cbx_lpm_add_sub 2003:11:17:16:32:08:SJ cbx_lpm_compare 2003:09:10:10:27:44:SJ cbx_lpm_counter 2003:12:16:17:25:44:SJ cbx_lpm_decode 2003:03:25:17:43:04:SJ cbx_lpm_mux 2003:10:21:14:09:22:SJ cbx_mgl 2004:01:13:14:00:54:SJ cbx_stratix 2003:12:15:10:23:28:SJ cbx_stratixii 2003:11:06:16:12:54:SJ cbx_util 2003:12:05:10:31:30:SJ VERSION_END
-- Copyright (C) 1988-2004 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only
-- to program PLD devices (but not masked PLD devices) from Altera. Any
-- other use of such megafunction design, netlist, support information,
-- device programming or simulation file, or any other related documentation
-- or information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to the
-- intellectual property, including patents, copyrights, trademarks, trade
-- secrets, or maskworks, embodied in any such megafunction design, netlist,
-- support information, device programming or simulation file, or any other
-- related documentation or information provided by Altera or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.
FUNCTION altsyncram_o8m (address_a[1..0], address_b[1..0], clock0, clock1, clocken0, clocken1, data_a[13..0], wren_a)
RETURNS ( q_b[13..0]);
FUNCTION add_sub_a0a (dataa[1..0], datab[1..0])
RETURNS ( result[1..0]);
FUNCTION lpm_counter (aclr, aload, aset, cin, clk_en, clock, cnt_en, data[LPM_WIDTH-1..0], sclr, sload, sset, updown)
WITH ( lpm_avalue, lpm_direction, lpm_modulus, lpm_svalue, lpm_width)
RETURNS ( cout, eq[15..0], q[LPM_WIDTH-1..0]);
--synthesis_resources = lpm_counter 1 lut 4 ram_bits (auto) 42
SUBDESIGN shift_taps_2ed
(
clken : input;
clock : input;
shiftin[13..0] : input;
shiftout[13..0] : output;
taps[13..0] : output;
)
VARIABLE
altsyncram4 : altsyncram_o8m;
dffe3a[1..0] : dffe;
add_sub2 : add_sub_a0a;
cntr1 : lpm_counter
WITH (
lpm_direction = "UP",
lpm_modulus = 3,
lpm_width = 2
);
rdaddress[1..0] : WIRE;
BEGIN
altsyncram4.address_a[] = cntr1.q[];
altsyncram4.address_b[] = rdaddress[];
altsyncram4.clock0 = clock;
altsyncram4.clock1 = clock;
altsyncram4.clocken0 = clken;
altsyncram4.clocken1 = clken;
altsyncram4.data_a[] = ( shiftin[]);
altsyncram4.wren_a = B"1";
dffe3a[].CLK = clock;
dffe3a[].D = ( (! add_sub2.result[1..1]), add_sub2.result[0..0]);
dffe3a[].ENA = clken;
add_sub2.dataa[] = cntr1.q[];
add_sub2.datab[] = B"00";
cntr1.clk_en = clken;
cntr1.clock = clock;
rdaddress[] = ( (! dffe3a[1..1].Q), dffe3a[0..0].Q);
shiftout[13..0] = altsyncram4.q_b[13..0];
taps[] = altsyncram4.q_b[];
END;
--VALID FILE
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