📄 mul.map.rpt
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Analysis & Synthesis report for mul
Mon Dec 19 22:28:26 2005
Version 4.0 Build 190 1/28/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Default Parameter Settings
5. Hierarchy
6. State Machine - state
7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis Equations
9. Analysis & Synthesis Files Read
10. Analysis & Synthesis Resource Usage Summary
11. WYSIWYG Cells
12. General Register Statistics
13. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+---------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+---------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Dec 19 22:28:26 2005 ;
; Revision Name ; mul ;
; Top-level Entity Name ; mul ;
; Family ; Stratix ;
; Total logic elements ; 109 ;
; Total pins ; 34 ;
; Total memory bits ; 0 ;
; DSP block 9-bit elements ; 0 ;
; Total PLLs ; 0 ;
; Total DLLs ; 0 ;
+-----------------------------+---------------------------------------+
+----------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+-----------------------------------------------------------------------------------------
; Option ; Setting ; Default Value ;
+---------------------------------------------------------+--------------+---------------+
; Top-level entity name ; mul ; ;
; Auto Resource Sharing ; Off ; Off ;
; Auto RAM Block Balancing ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Perform gate-level register retiming ; Off ; Off ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Remove Duplicate Logic ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Auto Carry Chains ; On ; On ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II ; 70 ; 70 ;
; Optimization Technique -- Stratix/Stratix GX ; Balanced ; Balanced ;
; Auto Global Register Control Signals ; On ; On ;
; Auto Global Clock ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore CARRY Buffers ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Power-Up Don't Care ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; State Machine Processing ; Auto ; Auto ;
; Family name ; Stratix ; Stratix ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; Preserve fewer node names ; On ; On ;
; Disk space/compilation speed tradeoff ; Normal ; Normal ;
; Create Debugging Nodes for IP Cores ; off ; off ;
+---------------------------------------------------------+--------------+---------------+
+-------------------------------------------------+
; Analysis & Synthesis Default Parameter Settings ;
+--------------------------------------------------
; Name ; Setting ;
+--------------------+----------------------------+
; CARRY_CHAIN ; MANUAL ;
; CASCADE_CHAIN ; MANUAL ;
; OPTIMIZE_FOR_SPEED ; 5 ;
; STYLE ; FAST ;
+--------------------+----------------------------+
+------------+
; Hierarchy ;
+------------+
mul
+-------------------------------------------+
; State Machine - state ;
+--------------------------------------------
; Name ; state~12 ; state~11 ; state~10 ;
+----------+----------+----------+----------+
; state.s0 ; 0 ; 0 ; 0 ;
; state.s1 ; 0 ; 1 ; 1 ;
; state.s2 ; 1 ; 0 ; 1 ;
+----------+----------+----------+----------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Compilation Hierarchy Node ; Logic Cells ; Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+-----------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |mul ; 109 (109) ; 52 ; 0 ; 0 ; 0 ; 0 ; 0 ; 34 ; 0 ; 57 (57) ; 16 (16) ; 36 (36) ; 19 (19) ; |mul ;
+----------------------------+-------------+-----------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
+---------------------------------+
; Analysis & Synthesis Equations ;
+---------------------------------+
The equations can be found in G:/mydesign/fir31/mul/mul.map.eqn.
+---------------------------------+
; Analysis & Synthesis Files Read ;
+----------------------------------
; File Name ; Read ;
+-----------+---------------------+
; mul.vhd ; Read ;
+-----------+---------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------------------------------
; Resource ; Usage ;
+-------------------------------+-------------+
; Logic cells ; 109 ;
; Total combinational functions ; 93 ;
; Total registers ; 52 ;
; I/O pins ; 34 ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 52 ;
; Total fan-out ; 411 ;
; Average fan-out ; 2.87 ;
+-------------------------------+-------------+
+----------------------------------------------------------------+
; WYSIWYG Cells ;
+-----------------------------------------------------------------
; Statistic ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells ; 19 ;
; Number of synthesis-generated cells ; 90 ;
; Number of WYSIWYG LUTs ; 19 ;
; Number of synthesis-generated LUTs ; 74 ;
; Number of WYSIWYG registers ; 0 ;
; Number of synthesis-generated registers ; 52 ;
; Number of cells with combinational logic only ; 57 ;
; Number of cells with registers only ; 16 ;
; Number of cells with combinational logic and registers ; 36 ;
+--------------------------------------------------------+-------+
+----------------------------------------------+
; General Register Statistics ;
+-----------------------------------------------
; Statistic ; Value ;
+--------------------------------------+-------+
; Number of registers using SCLR ; 0 ;
; Number of registers using SLOAD ; 0 ;
; Number of registers using ACLR ; 0 ;
; Number of registers using ALOAD ; 0 ;
; Number of registers using CLK_ENABLE ; 15 ;
; Number of registers using OE ; 0 ;
; Number of registers using PRESET ; 0 ;
+--------------------------------------+-------+
+--------------------------------+
; Analysis & Synthesis Messages ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
Info: Processing started: Mon Dec 19 22:28:22 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off mul -c mul
Info: Found 3 design units and 1 entities in source file mul.vhd
Info: Found design unit 1: nine_bit_int
Info: Found design unit 2: mul-a
Info: Found entity 1: mul
Info: State machine |mul|state contains 3 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine |mul|state
Info: Encoding result for state machine |mul|state
Info: Completed encoding using 3 state bits
Info: Encoded state bit state~12
Info: Encoded state bit state~11
Info: Encoded state bit state~10
Info: State |mul|state.s0 uses code string 000
Info: State |mul|state.s1 uses code string 011
Info: State |mul|state.s2 uses code string 101
Info: Implemented 143 device resources after synthesis - the final resource count might be different
Info: Implemented 19 input pins
Info: Implemented 15 output pins
Info: Implemented 109 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
Info: Processing ended: Mon Dec 19 22:28:26 2005
Info: Elapsed time: 00:00:03
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