📄 dff1.tan.rpt
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Timing Analyzer report for dff1
Mon Dec 12 21:11:00 2005
Version 4.0 Build 190 1/28/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Settings
3. Timing Analyzer Summary
4. Clock Settings Summary
5. tsu
6. tco
7. th
8. Minimum tco
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-----------------------------------------------------------------------------------------
; Option ; Setting ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name ; EP1S10B672C6 ; ; ;
; Report IO Paths Separately ; Off ; ; ;
; Ignore user-defined clock settings ; Off ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ;
; Cut off feedback from I/O pins ; On ; ; ;
; Cut off clear and preset signal paths ; On ; ; ;
; Cut off read during write signal paths ; On ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ;
; Run Minimum Analysis ; On ; ; ;
; Use Minimum Timing Models ; Off ; ; ;
; Number of paths to report ; 200 ; ; ;
; Number of destination nodes to report ; 10 ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ;
+-------------------------------------------------------+--------------------+------+----+
+--------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+---------------------------------------------------------------------------------------------
; Type ; Slack ; Required Time ; Actual Time ; From ; To ;
+------------------------+-------+---------------+-------------+--------------+--------------+
; Worst-case tsu ; N/A ; None ; 2.215 ns ; din[7] ; qout[7]~reg0 ;
; Worst-case tco ; N/A ; None ; 7.306 ns ; qout[2]~reg0 ; qout[2] ;
; Worst-case th ; N/A ; None ; -1.551 ns ; din[4] ; qout[4]~reg0 ;
; Worst-case minimum tco ; N/A ; None ; 6.455 ns ; qout[5]~reg0 ; qout[5] ;
+------------------------+-------+---------------+-------------+--------------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+---------------------------------------------------------------------------------------------------------------------------------------
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; clk ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
+----------------------------------------------------------------------+
; tsu ;
+-----------------------------------------------------------------------
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+--------+--------------+----------+
; N/A ; None ; 2.215 ns ; din[7] ; qout[7]~reg0 ; clk ;
; N/A ; None ; 2.110 ns ; din[2] ; qout[2]~reg0 ; clk ;
; N/A ; None ; 1.950 ns ; din[5] ; qout[5]~reg0 ; clk ;
; N/A ; None ; 1.822 ns ; din[0] ; qout[0]~reg0 ; clk ;
; N/A ; None ; 1.779 ns ; din[1] ; qout[1]~reg0 ; clk ;
; N/A ; None ; 1.756 ns ; din[6] ; qout[6]~reg0 ; clk ;
; N/A ; None ; 1.707 ns ; din[3] ; qout[3]~reg0 ; clk ;
; N/A ; None ; 1.661 ns ; din[4] ; qout[4]~reg0 ; clk ;
+-------+--------------+------------+--------+--------------+----------+
+-------------------------------------------------------------------------+
; tco ;
+--------------------------------------------------------------------------
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A ; None ; 7.306 ns ; qout[2]~reg0 ; qout[2] ; clk ;
; N/A ; None ; 7.278 ns ; qout[3]~reg0 ; qout[3] ; clk ;
; N/A ; None ; 7.210 ns ; qout[6]~reg0 ; qout[6] ; clk ;
; N/A ; None ; 7.205 ns ; qout[7]~reg0 ; qout[7] ; clk ;
; N/A ; None ; 6.623 ns ; qout[4]~reg0 ; qout[4] ; clk ;
; N/A ; None ; 6.583 ns ; qout[0]~reg0 ; qout[0] ; clk ;
; N/A ; None ; 6.505 ns ; qout[1]~reg0 ; qout[1] ; clk ;
; N/A ; None ; 6.455 ns ; qout[5]~reg0 ; qout[5] ; clk ;
+-------+--------------+------------+--------------+---------+------------+
+----------------------------------------------------------------------------+
; th ;
+-----------------------------------------------------------------------------
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+--------+--------------+----------+
; N/A ; None ; -1.551 ns ; din[4] ; qout[4]~reg0 ; clk ;
; N/A ; None ; -1.597 ns ; din[3] ; qout[3]~reg0 ; clk ;
; N/A ; None ; -1.646 ns ; din[6] ; qout[6]~reg0 ; clk ;
; N/A ; None ; -1.669 ns ; din[1] ; qout[1]~reg0 ; clk ;
; N/A ; None ; -1.712 ns ; din[0] ; qout[0]~reg0 ; clk ;
; N/A ; None ; -1.840 ns ; din[5] ; qout[5]~reg0 ; clk ;
; N/A ; None ; -2.000 ns ; din[2] ; qout[2]~reg0 ; clk ;
; N/A ; None ; -2.105 ns ; din[7] ; qout[7]~reg0 ; clk ;
+---------------+-------------+-----------+--------+--------------+----------+
+-----------------------------------------------------------------------------------------+
; Minimum tco ;
+------------------------------------------------------------------------------------------
; Minimum Slack ; Required Min tco ; Actual Min tco ; From ; To ; From Clock ;
+---------------+------------------+----------------+--------------+---------+------------+
; N/A ; None ; 6.455 ns ; qout[5]~reg0 ; qout[5] ; clk ;
; N/A ; None ; 6.505 ns ; qout[1]~reg0 ; qout[1] ; clk ;
; N/A ; None ; 6.583 ns ; qout[0]~reg0 ; qout[0] ; clk ;
; N/A ; None ; 6.623 ns ; qout[4]~reg0 ; qout[4] ; clk ;
; N/A ; None ; 7.205 ns ; qout[7]~reg0 ; qout[7] ; clk ;
; N/A ; None ; 7.210 ns ; qout[6]~reg0 ; qout[6] ; clk ;
; N/A ; None ; 7.278 ns ; qout[3]~reg0 ; qout[3] ; clk ;
; N/A ; None ; 7.306 ns ; qout[2]~reg0 ; qout[2] ; clk ;
+---------------+------------------+----------------+--------------+---------+------------+
+---------------------------+
; Timing Analyzer Messages ;
+---------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
Info: Processing started: Mon Dec 12 21:10:58 2005
Info: Command: quartus_tan --import_settings_files=on --export_settings_files=off dff1 -c dff1 --speed=6
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node clk is an undefined clock
Info: No valid register-to-register paths exist for clock clk
Info: tsu for register qout[7]~reg0 (data pin = din[7], clock pin = clk) is 2.215 ns
Info: + Longest pin to register delay is 5.154 ns
Info: 1: + IC(0.000 ns) + CELL(0.976 ns) = 0.976 ns; Loc. = Pin_E5; Fanout = 1; PIN Node = 'din[7]'
Info: 2: + IC(4.088 ns) + CELL(0.090 ns) = 5.154 ns; Loc. = LC_X5_Y30_N2; Fanout = 1; REG Node = 'qout[7]~reg0'
Info: Total cell delay = 1.066 ns ( 20.68 % )
Info: Total interconnect delay = 4.088 ns ( 79.32 % )
Info: + Micro setup delay of destination is 0.010 ns
Info: - Shortest clock path from clock clk to destination register is 2.949 ns
Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 8; CLK Node = 'clk'
Info: 2: + IC(1.727 ns) + CELL(0.560 ns) = 2.949 ns; Loc. = LC_X5_Y30_N2; Fanout = 1; REG Node = 'qout[7]~reg0'
Info: Total cell delay = 1.222 ns ( 41.44 % )
Info: Total interconnect delay = 1.727 ns ( 58.56 % )
Info: tco from clock clk to destination pin qout[2] through register qout[2]~reg0 is 7.306 ns
Info: + Longest clock path from clock clk to source register is 3.048 ns
Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 8; CLK Node = 'clk'
Info: 2: + IC(1.826 ns) + CELL(0.560 ns) = 3.048 ns; Loc. = LC_X9_Y1_N2; Fanout = 1; REG Node = 'qout[2]~reg0'
Info: Total cell delay = 1.222 ns ( 40.09 % )
Info: Total interconnect delay = 1.826 ns ( 59.91 % )
Info: + Micro clock to output delay of source is 0.176 ns
Info: + Longest register to pin delay is 4.082 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y1_N2; Fanout = 1; REG Node = 'qout[2]~reg0'
Info: 2: + IC(1.324 ns) + CELL(2.758 ns) = 4.082 ns; Loc. = Pin_W9; Fanout = 0; PIN Node = 'qout[2]'
Info: Total cell delay = 2.758 ns ( 67.56 % )
Info: Total interconnect delay = 1.324 ns ( 32.44 % )
Info: th for register qout[4]~reg0 (data pin = din[4], clock pin = clk) is -1.551 ns
Info: + Longest clock path from clock clk to destination register is 3.045 ns
Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 8; CLK Node = 'clk'
Info: 2: + IC(1.823 ns) + CELL(0.560 ns) = 3.045 ns; Loc. = LC_X1_Y2_N3; Fanout = 1; REG Node = 'qout[4]~reg0'
Info: Total cell delay = 1.222 ns ( 40.13 % )
Info: Total interconnect delay = 1.823 ns ( 59.87 % )
Info: + Micro hold delay of destination is 0.100 ns
Info: - Shortest pin to register delay is 4.696 ns
Info: 1: + IC(0.000 ns) + CELL(1.093 ns) = 1.093 ns; Loc. = Pin_AB3; Fanout = 1; PIN Node = 'din[4]'
Info: 2: + IC(3.513 ns) + CELL(0.090 ns) = 4.696 ns; Loc. = LC_X1_Y2_N3; Fanout = 1; REG Node = 'qout[4]~reg0'
Info: Total cell delay = 1.183 ns ( 25.19 % )
Info: Total interconnect delay = 3.513 ns ( 74.81 % )
Info: Minimum tco from clock clk to destination pin qout[5] through register qout[5]~reg0 is 6.455 ns
Info: + Shortest clock path from clock clk to source register is 2.877 ns
Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 8; CLK Node = 'clk'
Info: 2: + IC(1.655 ns) + CELL(0.560 ns) = 2.877 ns; Loc. = LC_X52_Y26_N8; Fanout = 1; REG Node = 'qout[5]~reg0'
Info: Total cell delay = 1.222 ns ( 42.47 % )
Info: Total interconnect delay = 1.655 ns ( 57.53 % )
Info: + Micro clock to output delay of source is 0.176 ns
Info: + Shortest register to pin delay is 3.402 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y26_N8; Fanout = 1; REG Node = 'qout[5]~reg0'
Info: 2: + IC(0.902 ns) + CELL(2.500 ns) = 3.402 ns; Loc. = Pin_K23; Fanout = 0; PIN Node = 'qout[5]'
Info: Total cell delay = 2.500 ns ( 73.49 % )
Info: Total interconnect delay = 0.902 ns ( 26.51 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Mon Dec 12 21:11:00 2005
Info: Elapsed time: 00:00:02
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