📄 dff1.fit.qmsg

📁 设计一个线性相位FIR滤波器（31阶）输入8位
💻 QMSG
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 12 14:26:35 2005 " "Info: Processing started: Mon Dec 12 14:26:35 2005" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --import_settings_files=off --export_settings_files=off dff1 -c dff1 " "Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off dff1 -c dff1" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "dff1 EP1S10B672C6 " "Info: Selected device EP1S10B672C6 for design dff1" {  } {  } 0}
{ "Info" "IFYGR_FYGR_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFYGR_FYGR_MIGRATION_NOT_SELECTED_SUB" "EP1S20B672C6 " "Info: Device EP1S20B672C6 is compatible" {  } {  } 2} { "Info" "IFYGR_FYGR_MIGRATION_NOT_SELECTED_SUB" "EP1S25B672C6 " "Info: Device EP1S25B672C6 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "18 18 " "Info: No exact pin location assignment(s) for 18 pins of 18 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "qout\[7\] " "Info: Pin qout\[7\] not assigned to an exact location on the device" {  } { { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 6 -1 0 } } { "g:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus/bin/Assignment Editor.qase" 1 { { 0 "qout\[7\]" } } } } { "g:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "g:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "g:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { qout[7] } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.fld" "" "" { Floorplan "g:/qdesigns/dff1/dff1.fld" "" "" { qout[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "qout\[6\] " "Info: Pin qout\[6\] not assigned to an exact location on the device" {  } { { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 6 -1 0 } } { "g:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus/bin/Assignment Editor.qase" 1 { { 0 "qout\[6\]" } } } } { "g:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "g:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "g:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { qout[6] } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.fld" "" "" { Floorplan "g:/qdesigns/dff1/dff1.fld" "" "" { qout[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "qout\[5\] " "Info: Pin qout\[5\] not assigned to an exact location on the device" {  } { { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 6 -1 0 } } { "g:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus/bin/Assignment Editor.qase" 1 { { 0 "qout\[5\]" } } } } { "g:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "g:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "g:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { qout[5] } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.fld" "" "" { Floorplan "g:/qdesigns/dff1/dff1.fld" "" "" { qout[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "qout\[4\] " "Info: Pin qout\[4\] not assigned to an exact location on the device" {  } { { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 6 -1 0 } } { "g:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus/bin/Assignment Editor.qase" 1 { { 0 "qout\[4\]" } } } } { "g:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "g:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "g:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { qout[4] } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.fld" "" "" { Floorplan "g:/qdesigns/dff1/dff1.fld" "" "" { qout[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "qout\[3\] " "Info: Pin qout\[3\] not assigned to an exact location on the device" {  } { { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 6 -1 0 } } { "g:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus/bin/Assignment Editor.qase" 1 { { 0 "qout\[3\]" } } } } { "g:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "g:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "g:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { qout[3] } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.fld" "" "" { Floorplan "g:/qdesigns/dff1/dff1.fld" "" "" { qout[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "qout\[2\] " "Info: Pin qout\[2\] not assigned to an exact location on the device" {  } { { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 6 -1 0 } } { "g:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus/bin/Assignment Editor.qase" 1 { { 0 "qout\[2\]" } } } } { "g:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "g:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "g:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { qout[2] } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.fld" "" "" { Floorplan "g:/qdesigns/dff1/dff1.fld" "" "" { qout[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "qout\[1\] " "Info: Pin qout\[1\] not assigned to an exact location on the device" {  } { { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 6 -1 0 } } { "g:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus/bin/Assignment Editor.qase" 1 { { 0 "qout\[1\]" } } } } { "g:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "g:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "g:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { qout[1] } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.fld" "" "" { Floorplan "g:/qdesigns/dff1/dff1.fld" "" "" { qout[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "qout\[0\] " "Info: Pin qout\[0\] not assigned to an exact location on the device" {  } { { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 6 -1 0 } } { "g:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus/bin/Assignment Editor.qase" 1 { { 0 "qout\[0\]" } } } } { "g:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "g:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "g:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { qout[0] } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.fld" "" "" { Floorplan "g:/qdesigns/dff1/dff1.fld" "" "" { qout[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "din\[7\] " "Info: Pin din\[7\] not assigned to an exact location on the device" {  } { { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 5 -1 0 } } { "g:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus/bin/Assignment Editor.qase" 1 { { 0 "din\[7\]" } } } } { "g:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "g:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "g:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { din[7] } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.fld" "" "" { Floorplan "g:/qdesigns/dff1/dff1.fld" "" "" { din[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clk " "Info: Pin clk not assigned to an exact location on the device" {  } { { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 4 -1 0 } } { "g:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "g:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "g:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "g:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.fld" "" "" { Floorplan "g:/qdesigns/dff1/dff1.fld" "" "" { clk } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "r " "Info: Pin r not assigned to an exact location on the device" {  } { { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 4 -1 0 } } { "g:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus/bin/Assignment Editor.qase" 1 { { 0 "r" } } } } { "g:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "g:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "g:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { r } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.fld" "" "" { Floorplan "g:/qdesigns/dff1/dff1.fld" "" "" { r } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "din\[6\] " "Info: Pin din\[6\] not assigned to an exact location on the device" {  } { { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 5 -1 0 } } { "g:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus/bin/Assignment Editor.qase" 1 { { 0 "din\[6\]" } } } } { "g:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "g:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "g:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { din[6] } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.fld" "" "" { Floorplan "g:/qdesigns/dff1/dff1.fld" "" "" { din[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "din\[5\] " "Info: Pin din\[5\] not assigned to an exact location on the device" {  } { { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 5 -1 0 } } { "g:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus/bin/Assignment Editor.qase" 1 { { 0 "din\[5\]" } } } } { "g:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "g:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "g:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { din[5] } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.fld" "" "" { Floorplan "g:/qdesigns/dff1/dff1.fld" "" "" { din[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "din\[4\] " "Info: Pin din\[4\] not assigned to an exact location on the device" {  } { { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 5 -1 0 } } { "g:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus/bin/Assignment Editor.qase" 1 { { 0 "din\[4\]" } } } } { "g:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "g:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "g:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { din[4] } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.fld" "" "" { Floorplan "g:/qdesigns/dff1/dff1.fld" "" "" { din[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "din\[3\] " "Info: Pin din\[3\] not assigned to an exact location on the device" {  } { { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 5 -1 0 } } { "g:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus/bin/Assignment Editor.qase" 1 { { 0 "din\[3\]" } } } } { "g:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "g:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "g:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { din[3] } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.fld" "" "" { Floorplan "g:/qdesigns/dff1/dff1.fld" "" "" { din[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "din\[2\] " "Info: Pin din\[2\] not assigned to an exact location on the device" {  } { { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 5 -1 0 } } { "g:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus/bin/Assignment Editor.qase" 1 { { 0 "din\[2\]" } } } } { "g:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "g:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "g:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { din[2] } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.fld" "" "" { Floorplan "g:/qdesigns/dff1/dff1.fld" "" "" { din[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "din\[1\] " "Info: Pin din\[1\] not assigned to an exact location on the device" {  } { { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 5 -1 0 } } { "g:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus/bin/Assignment Editor.qase" 1 { { 0 "din\[1\]" } } } } { "g:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "g:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "g:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { din[1] } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.fld" "" "" { Floorplan "g:/qdesigns/dff1/dff1.fld" "" "" { din[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "din\[0\] " "Info: Pin din\[0\] not assigned to an exact location on the device" {  } { { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 5 -1 0 } } { "g:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "g:/quartus/bin/Assignment Editor.qase" 1 { { 0 "din\[0\]" } } } } { "g:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "g:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "g:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { din[0] } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.fld" "" "" { Floorplan "g:/qdesigns/dff1/dff1.fld" "" "" { din[0] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_PERIOD_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing all clocks equally to maximize operation frequency" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on non-logic cell registers with location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in Pin M24 " "Info: Automatically promoted signal clk to use Global clock in Pin M24" {  } { { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 4 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "r Global clock in Pin M26 " "Info: Automatically promoted signal r to use Global clock in Pin M26" {  } { { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 4 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start DSP Scan-chain Inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Completed DSP scan-chain inferencing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density" {  } {  } 0}
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