dff1.tan.qmsg

设计一个线性相位FIR滤波器（31阶） 输入8位

{ "Info" "ITDB_TSU_RESULT" "qout\[7\]~reg0 din\[7\] clk 2.215 ns register " "Info: tsu for register qout\[7\]~reg0 (data pin = din\[7\], clock pin = clk) is 2.215 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.154 ns + Longest pin register " "Info: + Longest pin to register delay is 5.154 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.976 ns) 0.976 ns din\[7\] 1 PIN Pin_E5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.976 ns) = 0.976 ns; Loc. = Pin_E5; Fanout = 1; PIN Node = 'din\[7\]'" {  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { din[7] } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.088 ns) + CELL(0.090 ns) 5.154 ns qout\[7\]~reg0 2 REG LC_X5_Y30_N2 1 " "Info: 2: + IC(4.088 ns) + CELL(0.090 ns) = 5.154 ns; Loc. = LC_X5_Y30_N2; Fanout = 1; REG Node = 'qout\[7\]~reg0'" {  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "4.178 ns" { din[7] qout[7]~reg0 } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.066 ns 20.68 % " "Info: Total cell delay = 1.066 ns ( 20.68 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.088 ns 79.32 % " "Info: Total interconnect delay = 4.088 ns ( 79.32 % )" {  } {  } 0}  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "5.154 ns" { din[7] qout[7]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.949 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 2.949 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clk 1 CLK Pin_M24 8 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 8; CLK Node = 'clk'" {  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.727 ns) + CELL(0.560 ns) 2.949 ns qout\[7\]~reg0 2 REG LC_X5_Y30_N2 1 " "Info: 2: + IC(1.727 ns) + CELL(0.560 ns) = 2.949 ns; Loc. = LC_X5_Y30_N2; Fanout = 1; REG Node = 'qout\[7\]~reg0'" {  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "2.287 ns" { clk qout[7]~reg0 } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns 41.44 % " "Info: Total cell delay = 1.222 ns ( 41.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.727 ns 58.56 % " "Info: Total interconnect delay = 1.727 ns ( 58.56 % )" {  } {  } 0}  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "2.949 ns" { clk qout[7]~reg0 } "NODE_NAME" } } }  } 0}  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "5.154 ns" { din[7] qout[7]~reg0 } "NODE_NAME" } } } { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "2.949 ns" { clk qout[7]~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk qout\[2\] qout\[2\]~reg0 7.306 ns register " "Info: tco from clock clk to destination pin qout\[2\] through register qout\[2\]~reg0 is 7.306 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.048 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 3.048 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clk 1 CLK Pin_M24 8 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 8; CLK Node = 'clk'" {  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.826 ns) + CELL(0.560 ns) 3.048 ns qout\[2\]~reg0 2 REG LC_X9_Y1_N2 1 " "Info: 2: + IC(1.826 ns) + CELL(0.560 ns) = 3.048 ns; Loc. = LC_X9_Y1_N2; Fanout = 1; REG Node = 'qout\[2\]~reg0'" {  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "2.386 ns" { clk qout[2]~reg0 } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns 40.09 % " "Info: Total cell delay = 1.222 ns ( 40.09 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.826 ns 59.91 % " "Info: Total interconnect delay = 1.826 ns ( 59.91 % )" {  } {  } 0}  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "3.048 ns" { clk qout[2]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.082 ns + Longest register pin " "Info: + Longest register to pin delay is 4.082 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns qout\[2\]~reg0 1 REG LC_X9_Y1_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y1_N2; Fanout = 1; REG Node = 'qout\[2\]~reg0'" {  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { qout[2]~reg0 } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.324 ns) + CELL(2.758 ns) 4.082 ns qout\[2\] 2 PIN Pin_W9 0 " "Info: 2: + IC(1.324 ns) + CELL(2.758 ns) = 4.082 ns; Loc. = Pin_W9; Fanout = 0; PIN Node = 'qout\[2\]'" {  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "4.082 ns" { qout[2]~reg0 qout[2] } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.758 ns 67.56 % " "Info: Total cell delay = 2.758 ns ( 67.56 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.324 ns 32.44 % " "Info: Total interconnect delay = 1.324 ns ( 32.44 % )" {  } {  } 0}  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "4.082 ns" { qout[2]~reg0 qout[2] } "NODE_NAME" } } }  } 0}  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "3.048 ns" { clk qout[2]~reg0 } "NODE_NAME" } } } { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "4.082 ns" { qout[2]~reg0 qout[2] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "qout\[4\]~reg0 din\[4\] clk -1.551 ns register " "Info: th for register qout\[4\]~reg0 (data pin = din\[4\], clock pin = clk) is -1.551 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.045 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 3.045 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clk 1 CLK Pin_M24 8 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 8; CLK Node = 'clk'" {  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.823 ns) + CELL(0.560 ns) 3.045 ns qout\[4\]~reg0 2 REG LC_X1_Y2_N3 1 " "Info: 2: + IC(1.823 ns) + CELL(0.560 ns) = 3.045 ns; Loc. = LC_X1_Y2_N3; Fanout = 1; REG Node = 'qout\[4\]~reg0'" {  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "2.383 ns" { clk qout[4]~reg0 } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns 40.13 % " "Info: Total cell delay = 1.222 ns ( 40.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.823 ns 59.87 % " "Info: Total interconnect delay = 1.823 ns ( 59.87 % )" {  } {  } 0}  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "3.045 ns" { clk qout[4]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.696 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.696 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.093 ns) 1.093 ns din\[4\] 1 PIN Pin_AB3 1 " "Info: 1: + IC(0.000 ns) + CELL(1.093 ns) = 1.093 ns; Loc. = Pin_AB3; Fanout = 1; PIN Node = 'din\[4\]'" {  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { din[4] } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.513 ns) + CELL(0.090 ns) 4.696 ns qout\[4\]~reg0 2 REG LC_X1_Y2_N3 1 " "Info: 2: + IC(3.513 ns) + CELL(0.090 ns) = 4.696 ns; Loc. = LC_X1_Y2_N3; Fanout = 1; REG Node = 'qout\[4\]~reg0'" {  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "3.603 ns" { din[4] qout[4]~reg0 } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.183 ns 25.19 % " "Info: Total cell delay = 1.183 ns ( 25.19 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.513 ns 74.81 % " "Info: Total interconnect delay = 3.513 ns ( 74.81 % )" {  } {  } 0}  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "4.696 ns" { din[4] qout[4]~reg0 } "NODE_NAME" } } }  } 0}  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "3.045 ns" { clk qout[4]~reg0 } "NODE_NAME" } } } { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "4.696 ns" { din[4] qout[4]~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk qout\[5\] qout\[5\]~reg0 6.455 ns register " "Info: Minimum tco from clock clk to destination pin qout\[5\] through register qout\[5\]~reg0 is 6.455 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.877 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 2.877 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.662 ns) 0.662 ns clk 1 CLK Pin_M24 8 " "Info: 1: + IC(0.000 ns) + CELL(0.662 ns) = 0.662 ns; Loc. = Pin_M24; Fanout = 8; CLK Node = 'clk'" {  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.655 ns) + CELL(0.560 ns) 2.877 ns qout\[5\]~reg0 2 REG LC_X52_Y26_N8 1 " "Info: 2: + IC(1.655 ns) + CELL(0.560 ns) = 2.877 ns; Loc. = LC_X52_Y26_N8; Fanout = 1; REG Node = 'qout\[5\]~reg0'" {  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "2.215 ns" { clk qout[5]~reg0 } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns 42.47 % " "Info: Total cell delay = 1.222 ns ( 42.47 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.655 ns 57.53 % " "Info: Total interconnect delay = 1.655 ns ( 57.53 % )" {  } {  } 0}  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "2.877 ns" { clk qout[5]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.402 ns + Shortest register pin " "Info: + Shortest register to pin delay is 3.402 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns qout\[5\]~reg0 1 REG LC_X52_Y26_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X52_Y26_N8; Fanout = 1; REG Node = 'qout\[5\]~reg0'" {  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "" { qout[5]~reg0 } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.902 ns) + CELL(2.500 ns) 3.402 ns qout\[5\] 2 PIN Pin_K23 0 " "Info: 2: + IC(0.902 ns) + CELL(2.500 ns) = 3.402 ns; Loc. = Pin_K23; Fanout = 0; PIN Node = 'qout\[5\]'" {  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "3.402 ns" { qout[5]~reg0 qout[5] } "NODE_NAME" } } } { "g:/qdesigns/dff1/dff1.vhd" "" "" { Text "g:/qdesigns/dff1/dff1.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns 73.49 % " "Info: Total cell delay = 2.500 ns ( 73.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.902 ns 26.51 % " "Info: Total interconnect delay = 0.902 ns ( 26.51 % )" {  } {  } 0}  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "3.402 ns" { qout[5]~reg0 qout[5] } "NODE_NAME" } } }  } 0}  } { { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "2.877 ns" { clk qout[5]~reg0 } "NODE_NAME" } } } { "G:/qdesigns/dff1/db/dff1_cmp.qrpt" "" "" { Report "G:/qdesigns/dff1/db/dff1_cmp.qrpt" Compiler "dff1" "UNKNOWN" "V1" "G:/qdesigns/dff1/db/dff1.quartus_db" { Floorplan "" "" "3.402 ns" { qout[5]~reg0 qout[5] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 12 21:11:00 2005 " "Info: Processing ended: Mon Dec 12 21:11:00 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}