dff1.vhd

设计一个线性相位FIR滤波器（31阶） 输入8位

library ieee;
use ieee.std_logic_1164.all;
entity dff1 is
 port(r,clk:in std_logic;
      din:in std_logic_vector(7 downto 0);
      qout:out std_logic_vector(7 downto 0));
end ;
architecture rtl of dff1 is
begin
process(clk,r)
begin
 if r='1' then qout<="00000000";
   elsif (clk'event and clk='1') then
         qout<=din;
 end if;
end process;         
 end rtl;