📄 fir31_1.vwf

📁 设计一个线性相位FIR滤波器（31阶）输入8位
💻 VWF
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	PRINT_OPTIONS = "Print_options_version 6\
range_start 0ps\
range_end 400.0us\
width 1\
names_percentage 25\
comments 1\
grid_lines 1\
time_bars 1\
name_every_page 0\
expand_groups 0\
print_all 1";
	SIMULATION_TIME = 400000.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("clk")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("clk_out")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("xin")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 8;
	LSB_INDEX = 0;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("xin[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "xin";
}

SIGNAL("xin[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "xin";
}

SIGNAL("xin[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "xin";
}

SIGNAL("xin[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "xin";
}

SIGNAL("xin[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "xin";
}

SIGNAL("xin[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "xin";
}

SIGNAL("xin[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "xin";
}

SIGNAL("xin[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "xin";
}

SIGNAL("y")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 8;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("y[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "y";
}

SIGNAL("y[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "y";
}

SIGNAL("y[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "y";
}

SIGNAL("y[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "y";
}

SIGNAL("y[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "y";
}

SIGNAL("y[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "y";
}

SIGNAL("y[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "y";
}

SIGNAL("y[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "y";
}

TRANSITION_LIST("clk")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
		NODE
		{
			REPEAT = 19998;
			LEVEL 1 FOR 10.0;
			LEVEL 0 FOR 10.0;
		}
		LEVEL 1 FOR 10.0;
		LEVEL 0 FOR 10.0;
	}
}

TRANSITION_LIST("clk_out")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 909;
			LEVEL 0 FOR 220.0;
			LEVEL 1 FOR 220.0;
		}
		LEVEL 0 FOR 40.0;
	}
}

TRANSITION_LIST("xin[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1805.0;
		LEVEL 1 FOR 395.0;
		LEVEL 0 FOR 4910.0;
		LEVEL 1 FOR 370.0;
		LEVEL 0 FOR 6615.0;
		LEVEL 1 FOR 425.0;
		LEVEL 0 FOR 385480.0;
	}
}

TRANSITION_LIST("xin[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1805.0;
		LEVEL 1 FOR 395.0;
		LEVEL 0 FOR 4910.0;
		LEVEL 1 FOR 370.0;
		LEVEL 0 FOR 6615.0;
		LEVEL 1 FOR 425.0;
		LEVEL 0 FOR 385480.0;
	}
}

TRANSITION_LIST("xin[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1805.0;
		LEVEL 1 FOR 395.0;
		LEVEL 0 FOR 1345.0;
		LEVEL 1 FOR 310.0;
		LEVEL 0 FOR 3255.0;
		LEVEL 1 FOR 370.0;
		LEVEL 0 FOR 6615.0;
		LEVEL 1 FOR 425.0;
		LEVEL 0 FOR 385480.0;
	}
}

TRANSITION_LIST("xin[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 360.0;
		LEVEL 0 FOR 3185.0;
		LEVEL 1 FOR 310.0;
		LEVEL 0 FOR 1475.0;
		LEVEL 1 FOR 375.0;
		LEVEL 0 FOR 1405.0;
		LEVEL 1 FOR 370.0;
		LEVEL 0 FOR 1380.0;
		LEVEL 1 FOR 290.0;
		LEVEL 0 FOR 1435.0;
		LEVEL 1 FOR 350.0;
		LEVEL 0 FOR 3160.0;
		LEVEL 1 FOR 425.0;
		LEVEL 0 FOR 385480.0;
	}
}

TRANSITION_LIST("xin[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 360.0;
		LEVEL 0 FOR 10225.0;
		LEVEL 1 FOR 350.0;
		LEVEL 0 FOR 1395.0;
		LEVEL 1 FOR 345.0;
		LEVEL 0 FOR 1420.0;
		LEVEL 1 FOR 425.0;
		LEVEL 0 FOR 1335.0;
		LEVEL 1 FOR 410.0;
		LEVEL 0 FOR 383735.0;
	}
}

TRANSITION_LIST("xin[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 360.0;
		LEVEL 0 FOR 4970.0;
		LEVEL 1 FOR 375.0;
		LEVEL 0 FOR 3155.0;
		LEVEL 1 FOR 290.0;
		LEVEL 0 FOR 390850.0;
	}
}

TRANSITION_LIST("xin[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 360.0;
		LEVEL 0 FOR 1445.0;
		LEVEL 1 FOR 395.0;
		LEVEL 0 FOR 1345.0;
		LEVEL 1 FOR 310.0;
		LEVEL 0 FOR 5005.0;
		LEVEL 1 FOR 290.0;
		LEVEL 0 FOR 1435.0;
		LEVEL 1 FOR 350.0;
		LEVEL 0 FOR 1395.0;
		LEVEL 1 FOR 345.0;
		LEVEL 0 FOR 387325.0;
	}
}

TRANSITION_LIST("xin[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 7110.0;
		LEVEL 1 FOR 370.0;
		LEVEL 0 FOR 1380.0;
		LEVEL 1 FOR 290.0;
		LEVEL 0 FOR 4945.0;
		LEVEL 1 FOR 425.0;
		LEVEL 0 FOR 385480.0;
	}
}

TRANSITION_LIST("y[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 1987.09;
		LEVEL 1 FOR 1320.0;
		LEVEL 0 FOR 1320.0;
		LEVEL 1 FOR 1320.0;
		LEVEL 0 FOR 2200.0;
		LEVEL 1 FOR 1760.0;
		LEVEL 0 FOR 3520.0;
		LEVEL 1 FOR 2200.0;
		LEVEL 0 FOR 4840.0;
		LEVEL 1 FOR 1760.0;
		LEVEL 0 FOR 2640.0;
		LEVEL 1 FOR 1320.0;
		LEVEL 0 FOR 1320.0;
		LEVEL 1 FOR 1320.0;
		LEVEL 0 FOR 371172.91;
	}
}

TRANSITION_LIST("y[6]")
{
	NODE
	{
		REPEAT = 1;
12 下一页
💿 文件大小 2581 K
👤 上传用户 babydog00
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#FIR #线性 #相位 #8位
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