top.v

来自「一个非常简单的cpu设计的原代码,是用verilog编写的」· Verilog 代码 · 共 34 行

//the relatively simple cpu 
//design by zhxj,2005.4

module top;
reg clk, rst;
wire[15:0]addr;
wire[4:0]addr1;
wire[10:0]addr2;
wire[7:0]data;
wire read,write;
wire [7:0]rambus;
wire [7:0]rombus;
assign addr1=addr[4:0];
assign addr2=addr[15:5];
assign data=(|addr[15:5])?rambus:rombus;
assign rambus=(write)?data:8'bzzzzzzzz;
cpu mcpu(data,clk, rst,read, write,addr);

ram mm(rambus,addr2,read,write);

rom mm2(addr1,read,rombus);

initial
begin
clk=1;
rst=0;
#5
rst=1; 
#3600 $stop;
end
always #20 clk=~clk;
endmodule