top.v

来自「一个非常简单的cpu设计的原代码,是用verilog编写的」· Verilog 代码 · 共 21 行

//the very simple cpu
//design by zhxj,2005.4

module top;
reg clk, rst;
wire [5:0] addr;
wire [7:0]data;
wire read;
simplecpu mcpu(data, rst, clk, read, addr);
mem mm(addr,read,data);
initial
 begin
clk=1;
rst=1;
#45
rst=0;
#5000 $stop;
end

always #20 clk=~clk;
endmodule