📄 car.rpt
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* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\zsl\new!!!!!!!!!\car.rpt
car
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--------- LC30 R_RUN
| +------- LC17 RWC0
| | +----- LC19 RWC1
| | | +--- LC20 RWC2
| | | | +- LC21 RWC3
| | | | |
| | | | | Other LABs fed by signals
| | | | | that feed LAB 'B'
LC | | | | | | A B C D | Logic cells that feed LAB 'B':
Pin
43 -> - - - - - | - - - - | <-- clkin
1 -> - - - - - | * - - - | <-- CLRn
LC9 -> - * * * * | * * * - | <-- WCCount2
LC3 -> - * * * * | * * * - | <-- WCCount1
LC2 -> - * * * * | * * * - | <-- WCCount0
LC50 -> * * * * * | - * * * | <-- Sensorstate2
LC52 -> * * * * * | - * - - | <-- Sensorstate1
LC49 -> * * * * * | - * * * | <-- Sensorstate0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\zsl\new!!!!!!!!!\car.rpt
car
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------- LC37 LWC0
| +----- LC36 LWC1
| | +--- LC35 LWC2
| | | +- LC33 LWC3
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'C'
LC | | | | | A B C D | Logic cells that feed LAB 'C':
Pin
43 -> - - - - | - - - - | <-- clkin
1 -> - - - - | * - - - | <-- CLRn
LC9 -> * * * * | * * * - | <-- WCCount2
LC3 -> * * * * | * * * - | <-- WCCount1
LC2 -> * * * * | * * * - | <-- WCCount0
LC50 -> * * * * | - * * * | <-- Sensorstate2
LC49 -> * * * * | - * * * | <-- Sensorstate0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\zsl\new!!!!!!!!!\car.rpt
car
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------- LC53 L_RUN
| +----- LC50 Sensorstate2
| | +--- LC52 Sensorstate1
| | | +- LC49 Sensorstate0
| | | |
| | | | Other LABs fed by signals
| | | | that feed LAB 'D'
LC | | | | | A B C D | Logic cells that feed LAB 'D':
LC50 -> * - - - | - * * * | <-- Sensorstate2
LC49 -> * - - - | - * * * | <-- Sensorstate0
Pin
43 -> - - - - | - - - - | <-- clkin
1 -> - - - - | * - - - | <-- CLRn
9 -> - - - * | - - - * | <-- iSensorState0
8 -> - - * - | - - - * | <-- iSensorState1
11 -> - * - - | - - - * | <-- iSensorState2
LC11 -> - * * * | - - - * | <-- Dclkout
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\zsl\new!!!!!!!!!\car.rpt
car
** EQUATIONS **
clkin : INPUT;
CLRn : INPUT;
iSensorState0 : INPUT;
iSensorState1 : INPUT;
iSensorState2 : INPUT;
-- Node name is 'Cclkout' = 'clk'
-- Equation name is 'Cclkout', location is LC001, type is output.
Cclkout = TFFE( _EQ001, GLOBAL( clkin), VCC, VCC, CLRn);
_EQ001 = count10 & !count11 & !count12 & count13;
-- Node name is ':19' = 'clk1'
-- Equation name is 'clk1', location is LC012, type is buried.
clk1 = TFFE( _EQ002, Cclkout, GLOBAL( CLRn), VCC, VCC);
_EQ002 = WCCount0 & WCCount1 & WCCount2;
-- Node name is ':40' = 'count10'
-- Equation name is 'count10', location is LC004, type is buried.
count10 = TFFE( VCC, GLOBAL( clkin), GLOBAL( CLRn), VCC, VCC);
-- Node name is ':39' = 'count11'
-- Equation name is 'count11', location is LC007, type is buried.
count11 = DFFE( _EQ003 $ _LC013, GLOBAL( clkin), GLOBAL( CLRn), VCC, VCC);
_EQ003 = count10 & !count11 & !count12 & count13 & _LC013;
-- Node name is ':38' = 'count12'
-- Equation name is 'count12', location is LC008, type is buried.
count12 = TFFE( _EQ004, GLOBAL( clkin), GLOBAL( CLRn), VCC, VCC);
_EQ004 = count10 & count11;
-- Node name is ':37' = 'count13'
-- Equation name is 'count13', location is LC010, type is buried.
count13 = DFFE( _EQ005 $ _LC005, GLOBAL( clkin), GLOBAL( CLRn), VCC, VCC);
_EQ005 = count10 & !count11 & !count12 & count13 & _LC005;
-- Node name is ':228' = 'count20'
-- Equation name is 'count20', location is LC014, type is buried.
count20 = TFFE( VCC, clk1, GLOBAL( CLRn), VCC, VCC);
-- Node name is ':227' = 'count21'
-- Equation name is 'count21', location is LC015, type is buried.
count21 = TFFE( count20, clk1, GLOBAL( CLRn), VCC, VCC);
-- Node name is ':226' = 'count22'
-- Equation name is 'count22', location is LC016, type is buried.
count22 = TFFE( _EQ006, clk1, GLOBAL( CLRn), VCC, VCC);
_EQ006 = count20 & count21;
-- Node name is 'Dclkout' = 'Dclk'
-- Equation name is 'Dclkout', location is LC011, type is output.
Dclkout = TFFE( _EQ007, clk1, GLOBAL( CLRn), VCC, VCC);
_EQ007 = count20 & count21 & count22;
-- Node name is 'L_RUN'
-- Equation name is 'L_RUN', location is LC053, type is output.
L_RUN = LCELL( _EQ008 $ !Sensorstate2);
_EQ008 = Sensorstate0 & Sensorstate2;
-- Node name is 'LWC0'
-- Equation name is 'LWC0', location is LC037, type is output.
LWC0 = LCELL( _EQ009 $ VCC);
_EQ009 = Sensorstate0 & !WCCount0 & !WCCount1 & !WCCount2
# !Sensorstate2 & !WCCount0 & !WCCount1 & !WCCount2
# Sensorstate0 & WCCount1 & WCCount2
# !Sensorstate2 & WCCount1 & WCCount2;
-- Node name is 'LWC1'
-- Equation name is 'LWC1', location is LC036, type is output.
LWC1 = LCELL( _EQ010 $ !WCCount2);
_EQ010 = WCCount0 & WCCount1 & WCCount2
# !Sensorstate0 & Sensorstate2 & WCCount2;
-- Node name is 'LWC2'
-- Equation name is 'LWC2', location is LC035, type is output.
LWC2 = LCELL( _EQ011 $ VCC);
_EQ011 = Sensorstate0 & !WCCount0 & !WCCount1 & WCCount2
# !Sensorstate2 & !WCCount0 & !WCCount1 & WCCount2
# Sensorstate0 & WCCount1 & !WCCount2
# !Sensorstate2 & WCCount1 & !WCCount2;
-- Node name is 'LWC3'
-- Equation name is 'LWC3', location is LC033, type is output.
LWC3 = LCELL( _EQ012 $ WCCount2);
_EQ012 = WCCount0 & WCCount1 & !WCCount2
# !Sensorstate0 & Sensorstate2 & !WCCount2;
-- Node name is 'R_RUN'
-- Equation name is 'R_RUN', location is LC030, type is output.
R_RUN = LCELL( _EQ013 $ Sensorstate2);
_EQ013 = !Sensorstate0 & Sensorstate1 & !Sensorstate2;
-- Node name is 'RWC0'
-- Equation name is 'RWC0', location is LC017, type is output.
RWC0 = LCELL( _EQ014 $ VCC);
_EQ014 = !Sensorstate0 & Sensorstate1 & WCCount0 & WCCount1 & WCCount2
# Sensorstate2 & WCCount0 & WCCount1 & WCCount2
# !Sensorstate0 & Sensorstate1 & !WCCount1 & !WCCount2
# Sensorstate2 & !WCCount1 & !WCCount2;
-- Node name is 'RWC1'
-- Equation name is 'RWC1', location is LC019, type is output.
RWC1 = LCELL( _EQ015 $ WCCount2);
_EQ015 = Sensorstate0 & !Sensorstate2 & !WCCount2
# !WCCount0 & !WCCount1 & !WCCount2
# !Sensorstate1 & !Sensorstate2 & !WCCount2;
-- Node name is 'RWC2'
-- Equation name is 'RWC2', location is LC020, type is output.
RWC2 = LCELL( _EQ016 $ VCC);
_EQ016 = !Sensorstate0 & Sensorstate1 & WCCount0 & WCCount1 & !WCCount2
# Sensorstate2 & WCCount0 & WCCount1 & !WCCount2
# !Sensorstate0 & Sensorstate1 & !WCCount1 & WCCount2
# Sensorstate2 & !WCCount1 & WCCount2;
-- Node name is 'RWC3'
-- Equation name is 'RWC3', location is LC021, type is output.
RWC3 = LCELL( _EQ017 $ !WCCount2);
_EQ017 = Sensorstate0 & !Sensorstate2 & WCCount2
# !WCCount0 & !WCCount1 & WCCount2
# !Sensorstate1 & !Sensorstate2 & WCCount2;
-- Node name is ':26' = 'Sensorstate0'
-- Equation name is 'Sensorstate0', location is LC049, type is buried.
Sensorstate0 = DFFE( iSensorState0 $ GND, Dclkout, GLOBAL( CLRn), VCC, VCC);
-- Node name is ':25' = 'Sensorstate1'
-- Equation name is 'Sensorstate1', location is LC052, type is buried.
Sensorstate1 = DFFE( iSensorState1 $ GND, Dclkout, GLOBAL( CLRn), VCC, VCC);
-- Node name is ':24' = 'Sensorstate2'
-- Equation name is 'Sensorstate2', location is LC050, type is buried.
Sensorstate2 = DFFE( iSensorState2 $ GND, Dclkout, GLOBAL( CLRn), VCC, VCC);
-- Node name is ':22' = 'WCCount0'
-- Equation name is 'WCCount0', location is LC002, type is buried.
WCCount0 = TFFE( VCC, Cclkout, GLOBAL( CLRn), VCC, VCC);
-- Node name is ':21' = 'WCCount1'
-- Equation name is 'WCCount1', location is LC003, type is buried.
WCCount1 = TFFE( WCCount0, Cclkout, GLOBAL( CLRn), VCC, VCC);
-- Node name is ':20' = 'WCCount2'
-- Equation name is 'WCCount2', location is LC009, type is buried.
WCCount2 = TFFE( _EQ018, Cclkout, GLOBAL( CLRn), VCC, VCC);
_EQ018 = WCCount0 & WCCount1;
-- Node name is '|LPM_ADD_SUB:68|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC013', type is buried
_LC013 = LCELL( count11 $ count10);
-- Node name is '|LPM_ADD_SUB:68|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC005', type is buried
_LC005 = LCELL( count13 $ _EQ019);
_EQ019 = count10 & count11 & count12;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\zsl\new!!!!!!!!!\car.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,265K
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