📄 car.rpt
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Project Information e:\zsl\new!!!!!!!!!\car.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 12/14/2004 18:30:12
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
CAR
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
car EPM7064SLC44-10 5 12 0 28 0 43 %
User Pins: 5 12 0
Project Information e:\zsl\new!!!!!!!!!\car.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clkin' chosen for auto global Clock
INFO: Signal 'CLRn' chosen for auto global Clear
Project Information e:\zsl\new!!!!!!!!!\car.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
car@43 clkin
car@1 CLRn
car@9 iSensorState0
car@8 iSensorState1
car@11 iSensorState2
car@37 L_RUN
car@27 LWC0
car@26 LWC1
car@25 LWC2
car@24 LWC3
car@14 R_RUN
car@21 RWC0
car@20 RWC1
car@19 RWC2
car@18 RWC3
Project Information e:\zsl\new!!!!!!!!!\car.rpt
** FILE HIERARCHY **
|lpm_add_sub:68|
|lpm_add_sub:68|addcore:adder|
|lpm_add_sub:68|addcore:adder|addcore:adder0|
|lpm_add_sub:68|altshift:result_ext_latency_ffs|
|lpm_add_sub:68|altshift:carry_ext_latency_ffs|
|lpm_add_sub:68|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:171|
|lpm_add_sub:171|addcore:adder|
|lpm_add_sub:171|addcore:adder|addcore:adder0|
|lpm_add_sub:171|altshift:result_ext_latency_ffs|
|lpm_add_sub:171|altshift:carry_ext_latency_ffs|
|lpm_add_sub:171|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:256|
|lpm_add_sub:256|addcore:adder|
|lpm_add_sub:256|addcore:adder|addcore:adder0|
|lpm_add_sub:256|altshift:result_ext_latency_ffs|
|lpm_add_sub:256|altshift:carry_ext_latency_ffs|
|lpm_add_sub:256|altshift:oflow_ext_latency_ffs|
Device-Specific Information: e:\zsl\new!!!!!!!!!\car.rpt
car
***** Logic for device 'car' compiled without errors.
Device: EPM7064SLC44-10
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffff
R R R R
D E E E E
c S S S S
l E E c E E
k R R C l R R
o V V V G L G k G V V
u E E C N R N i N E E
t D D C D n D n D D D
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
#TDI | 7 39 | RESERVED
iSensorState1 | 8 38 | #TDO
iSensorState0 | 9 37 | L_RUN
GND | 10 36 | RESERVED
iSensorState2 | 11 35 | VCC
Cclkout | 12 EPM7064SLC44-10 34 | RESERVED
#TMS | 13 33 | RESERVED
R_RUN | 14 32 | #TCK
VCC | 15 31 | RESERVED
RESERVED | 16 30 | GND
RESERVED | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V L L L L R
W W W W N C W W W W E
C C C C D C C C C C S
3 2 1 0 3 2 1 0 E
R
V
E
D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\zsl\new!!!!!!!!!\car.rpt
car
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 15/16( 93%) 6/ 8( 75%) 0/16( 0%) 15/36( 41%)
B: LC17 - LC32 5/16( 31%) 6/ 8( 75%) 0/16( 0%) 6/36( 16%)
C: LC33 - LC48 4/16( 25%) 5/ 8( 62%) 0/16( 0%) 5/36( 13%)
D: LC49 - LC64 4/16( 25%) 2/ 8( 25%) 0/16( 0%) 6/36( 16%)
Total dedicated input pins used: 2/4 ( 50%)
Total I/O pins used: 19/32 ( 59%)
Total logic cells used: 28/64 ( 43%)
Total shareable expanders used: 0/64 ( 0%)
Total Turbo logic cells used: 28/64 ( 43%)
Total shareable expanders not available (n/a): 0/64 ( 0%)
Average fan-in: 4.60
Total fan-in: 129
Total input pins required: 5
Total fast input logic cells required: 0
Total output pins required: 12
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 28
Total flipflops required: 16
Total product terms required: 68
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 64 ( 0%)
Device-Specific Information: e:\zsl\new!!!!!!!!!\car.rpt
car
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
43 - - INPUT G 0 0 0 0 0 0 0 clkin
1 - - INPUT G 0 0 0 0 0 1 0 CLRn
9 (4) (A) INPUT 0 0 0 0 0 0 1 iSensorState0
8 (5) (A) INPUT 0 0 0 0 0 0 1 iSensorState1
11 (3) (A) INPUT 0 0 0 0 0 0 1 iSensorState2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\zsl\new!!!!!!!!!\car.rpt
car
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
12 1 A FF + t 0 0 0 1 4 0 4 Cclkout (:18)
6 11 A FF t 0 0 0 0 4 0 3 Dclkout (:23)
37 53 D OUTPUT t 0 0 0 0 2 0 0 L_RUN
27 37 C OUTPUT t 0 0 0 0 5 0 0 LWC0
26 36 C OUTPUT t 0 0 0 0 5 0 0 LWC1
25 35 C OUTPUT t 0 0 0 0 5 0 0 LWC2
24 33 C OUTPUT t 0 0 0 0 5 0 0 LWC3
14 30 B OUTPUT t 0 0 0 0 3 0 0 R_RUN
21 17 B OUTPUT t 0 0 0 0 6 0 0 RWC0
20 19 B OUTPUT t 0 0 0 0 6 0 0 RWC1
19 20 B OUTPUT t 0 0 0 0 6 0 0 RWC2
18 21 B OUTPUT t 0 0 0 0 6 0 0 RWC3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\zsl\new!!!!!!!!!\car.rpt
car
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 13 A SOFT t 0 0 0 0 2 0 1 |LPM_ADD_SUB:68|addcore:adder|addcore:adder0|result_node1
(8) 5 A SOFT t 0 0 0 0 4 0 1 |LPM_ADD_SUB:68|addcore:adder|addcore:adder0|result_node3
- 12 A TFFE t 0 0 0 0 4 1 3 clk1 (:19)
- 9 A TFFE t 0 0 0 0 3 8 1 WCCount2 (:20)
(11) 3 A TFFE t 0 0 0 0 2 8 2 WCCount1 (:21)
- 2 A TFFE t 0 0 0 0 1 8 3 WCCount0 (:22)
- 50 D DFFE t 0 0 0 1 1 10 0 Sensorstate2 (:24)
(36) 52 D DFFE t 0 0 0 1 1 5 0 Sensorstate1 (:25)
(33) 49 D DFFE t 0 0 0 1 1 10 0 Sensorstate0 (:26)
- 10 A DFFE + t 0 0 0 0 5 1 3 count13 (:37)
(7) 8 A TFFE + t 0 0 0 0 2 1 3 count12 (:38)
- 7 A DFFE + t 0 0 0 0 5 1 5 count11 (:39)
(9) 4 A TFFE + t 0 0 0 0 0 1 5 count10 (:40)
(4) 16 A TFFE t 0 0 0 0 3 1 0 count22 (:226)
- 15 A TFFE t 0 0 0 0 2 1 1 count21 (:227)
(5) 14 A TFFE t 0 0 0 0 1 1 2 count20 (:228)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\zsl\new!!!!!!!!!\car.rpt
car
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----------------------------- LC1 Cclkout
| +--------------------------- LC11 Dclkout
| | +------------------------- LC13 |LPM_ADD_SUB:68|addcore:adder|addcore:adder0|result_node1
| | | +----------------------- LC5 |LPM_ADD_SUB:68|addcore:adder|addcore:adder0|result_node3
| | | | +--------------------- LC12 clk1
| | | | | +------------------- LC9 WCCount2
| | | | | | +----------------- LC3 WCCount1
| | | | | | | +--------------- LC2 WCCount0
| | | | | | | | +------------- LC10 count13
| | | | | | | | | +----------- LC8 count12
| | | | | | | | | | +--------- LC7 count11
| | | | | | | | | | | +------- LC4 count10
| | | | | | | | | | | | +----- LC16 count22
| | | | | | | | | | | | | +--- LC15 count21
| | | | | | | | | | | | | | +- LC14 count20
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'A':
LC1 -> * - - - * * * * - - - - - - - | * - - - | <-- Cclkout
LC13 -> - - - - - - - - - - * - - - - | * - - - | <-- |LPM_ADD_SUB:68|addcore:adder|addcore:adder0|result_node1
LC5 -> - - - - - - - - * - - - - - - | * - - - | <-- |LPM_ADD_SUB:68|addcore:adder|addcore:adder0|result_node3
LC12 -> - * - - * - - - - - - - * * * | * - - - | <-- clk1
LC9 -> - - - - * * - - - - - - - - - | * * * - | <-- WCCount2
LC3 -> - - - - * * * - - - - - - - - | * * * - | <-- WCCount1
LC2 -> - - - - * * * * - - - - - - - | * * * - | <-- WCCount0
LC10 -> * - - * - - - - * - * - - - - | * - - - | <-- count13
LC8 -> * - - * - - - - * * * - - - - | * - - - | <-- count12
LC7 -> * - * * - - - - * * * - - - - | * - - - | <-- count11
LC4 -> * - * * - - - - * * * * - - - | * - - - | <-- count10
LC16 -> - * - - - - - - - - - - * - - | * - - - | <-- count22
LC15 -> - * - - - - - - - - - - * * - | * - - - | <-- count21
LC14 -> - * - - - - - - - - - - * * * | * - - - | <-- count20
Pin
43 -> - - - - - - - - - - - - - - - | - - - - | <-- clkin
1 -> * - - - - - - - - - - - - - - | * - - - | <-- CLRn
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