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来自「VHDL写的LMS算法程序。利用本地正弦信号」· LOG 代码 · 共 1,677 行 · 第 1/5 页
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Started process "Check Syntax".=========================================================================* HDL Compilation *=========================================================================WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS2\FPGA_LMS/cosfunc.vhd. Ignore this file from project file lms_vhdl.prj.Compiling vhdl file F:/FPGA_LMS2/FPGA_LMS/LMS.vhd in Library work.Entity <lms> (Architecture <behav>) compiled.Completed process "Check Syntax".
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Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS2\FPGA_LMS/cosfunc.vhd. Ignore this file from project file lms_vhdl.prj.Compiling vhdl file F:/FPGA_LMS2/FPGA_LMS/LMS.vhd in Library work.Architecture behav of Entity lms is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <lms> (Architecture <behav>).WARNING:Xst:766 - F:/FPGA_LMS2/FPGA_LMS/LMS.vhd line 66: Generating a Black Box for component <cosfunc>.INFO:Xst:1304 - Contents of register <CE> in unit <lms> never changes during circuit operation. The register is replaced by logic.Entity <lms> analyzed. Unit <lms> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <lms>. Related source file is F:/FPGA_LMS2/FPGA_LMS/LMS.vhd. Found 8-bit register for signal <waveOut>. Found 8x8-bit multiplier for signal <$n0000> created at line 89. Found 8x8-bit multiplier for signal <$n0001> created at line 107. Found 8x8-bit multiplier for signal <$n0002> created at line 152. Found 8x8-bit multiplier for signal <$n0004> created at line 176. Found 8-bit subtractor for signal <$n0009> created at line 132. Found 8-bit adder for signal <$n0010> created at line 128. Found 1-bit register for signal <ACLR>. Found 8-bit register for signal <err>. Found 8-bit register for signal <Qcos>. Found 8-bit register for signal <Qsin>. Found 6-bit up counter for signal <sTHETA>. Found 8-bit up accumulator for signal <Wcos>. Found 8-bit up accumulator for signal <Wsin>. Summary: inferred 1 Counter(s). inferred 2 Accumulator(s). inferred 33 D-type flip-flop(s). inferred 2 Adder/Subtracter(s). inferred 4 Multiplier(s).Unit <lms> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Found registered multiplier on the signal <_n0000> with 1 register level(s).Found registered multiplier on the signal <_n0001> with 1 register level(s).Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Multipliers : 4 8x8-bit multiplier : 2 8x8-bit registered multiplier : 2# Adders/Subtractors : 2 8-bit adder : 1 8-bit subtractor : 1# Counters : 1 6-bit up counter : 1# Accumulators : 2 8-bit up accumulator : 2# Registers : 3 1-bit register : 1 8-bit register : 2==================================================================================================================================================* Low Level Synthesis *=========================================================================Launcher: "cosfunc.ngo" is up to date.Loading core <cosfunc> for timing and area information for instance <U1>.Optimizing unit <lms> ...Loading device for application Xst from file '2v1000.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block lms, actual ratio is 0.WARNING:Xst:382 - Register BU30 is equivalent to BU15WARNING:Xst:382 - Register BU32 is equivalent to BU17WARNING:Xst:382 - Register BU34 is equivalent to BU19WARNING:Xst:382 - Register BU36 is equivalent to BU21WARNING:Xst:382 - Register BU38 is equivalent to BU23WARNING:Xst:382 - Register BU40 is equivalent to BU25FlipFlop err_7 has been replicated 1 time(s)=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2v1000fg256-4 Number of Slices: 40 out of 5120 0% Number of Slice Flip Flops: 70 out of 10240 0% Number of 4 input LUTs: 42 out of 10240 0% Number of bonded IOBs: 25 out of 172 14% Number of BRAMs: 1 out of 40 2% Number of MULT18X18s: 4 out of 40 10% Number of GCLKs: 1 out of 16 6% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+CLK | BUFGP | 73 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4 Minimum period: 10.321ns (Maximum Frequency: 96.892MHz) Minimum input arrival time before clock: 4.041ns Maximum output required time after clock: 5.838ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
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Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS2\FPGA_LMS/cosfunc.vhd. Ignore this file from project file lms_vhdl.prj.Compiling vhdl file F:/FPGA_LMS2/FPGA_LMS/LMS.vhd in Library work.Entity <lms> (Architecture <behav>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <lms> (Architecture <behav>).WARNING:Xst:766 - F:/FPGA_LMS2/FPGA_LMS/LMS.vhd line 66: Generating a Black Box for component <cosfunc>.INFO:Xst:1304 - Contents of register <CE> in unit <lms> never changes during circuit operation. The register is replaced by logic.Entity <lms> analyzed. Unit <lms> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <lms>. Related source file is F:/FPGA_LMS2/FPGA_LMS/LMS.vhd. Found 8-bit register for signal <waveOut>. Found 8x8-bit multiplier for signal <$n0000> created at line 89. Found 8x8-bit multiplier for signal <$n0001> created at line 107. Found 8x8-bit multiplier for signal <$n0002> created at line 152. Found 8x8-bit multiplier for signal <$n0004> created at line 176. Found 8-bit subtractor for signal <$n0009> created at line 132. Found 8-bit adder for signal <$n0010> created at line 128. Found 1-bit register for signal <ACLR>. Found 8-bit register for signal <err>. Found 8-bit register for signal <Qcos>. Found 8-bit register for signal <Qsin>. Found 6-bit up counter for signal <sTHETA>. Found 8-bit up accumulator for signal <Wcos>. Found 8-bit up accumulator for signal <Wsin>. Summary: inferred 1 Counter(s). inferred 2 Accumulator(s). inferred 33 D-type flip-flop(s). inferred 2 Adder/Subtracter(s). inferred 4 Multiplier(s).Unit <lms> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Found registered multiplier on the signal <_n0000> with 1 register level(s).Found registered multiplier on the signal <_n0001> with 1 register level(s).Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Multipliers : 4 8x8-bit multiplier : 2 8x8-bit registered multiplier : 2# Adders/Subtractors : 2 8-bit adder : 1 8-bit subtractor : 1# Counters : 1 6-bit up counter : 1# Accumulators : 2 8-bit up accumulator : 2# Registers : 3 1-bit register : 1 8-bit register : 2==================================================================================================================================================* Low Level Synthesis *=========================================================================Launcher: "cosfunc.ngo" is up to date.Loading core <cosfunc> for timing and area information for instance <U1>.Optimizing unit <lms> ...Loading device for application Xst from file '2v1000.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block lms, actual ratio is 0.WARNING:Xst:382 - Register BU30 is equivalent to BU15WARNING:Xst:382 - Register BU32 is equivalent to BU17WARNING:Xst:382 - Register BU34 is equivalent to BU19WARNING:Xst:382 - Register BU36 is equivalent to BU21WARNING:Xst:382 - Register BU38 is equivalent to BU23WARNING:Xst:382 - Register BU40 is equivalent to BU25FlipFlop err_7 has been replicated 1 time(s)=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2v1000fg256-4 Number of Slices: 40 out of 5120 0% Number of Slice Flip Flops: 70 out of 10240 0% Number of 4 input LUTs: 42 out of 10240 0% Number of bonded IOBs: 25 out of 172 14% Number of BRAMs: 1 out of 40 2% Number of MULT18X18s: 4 out of 40 10% Number of GCLKs: 1 out of 16 6% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+CLK | BUFGP | 73 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4 Minimum period: 10.321ns (Maximum Frequency: 96.892MHz) Minimum input arrival time before clock: 4.041ns Maximum output required time after clock: 5.838ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
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