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来自「VHDL写的LMS算法程序。利用本地正弦信号」· LOG 代码 · 共 1,677 行 · 第 1/5 页

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WARNING: There is no design source which the test bench can be attached to.

Error creating testmux.vhd. Defaulting to boilerplate test bench.



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Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/LMS is now defined in a different file: was F:/FPGA_LMS/LMS.vhd, now is F:/FPGA_LMS2/FPGA_LMS/LMS.vhd
WARNING:HDLParsers:3215 - Unit work/LMS/BEHAV is now defined in a different file: was F:/FPGA_LMS/LMS.vhd, now is F:/FPGA_LMS2/FPGA_LMS/LMS.vhd
WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS2\FPGA_LMS/cosfunc.vhd. Ignore this file from project file lms_vhdl.prj.
Compiling vhdl file F:/FPGA_LMS2/FPGA_LMS/LMS.vhd in Library work.
ERROR:HDLParsers:3292 - F:/FPGA_LMS2/FPGA_LMS/LMS.vhd Line 90. + has two possible definitions in this scope.  For example, parameter 1 (result of operator) can be: std_logic_vector or SIGNED
ERROR:HDLParsers:1411 - F:/FPGA_LMS2/FPGA_LMS/LMS.vhd Line 95. Parameter waveOut of mode out can not be associated with a formal parameter of mode in.
ERROR: XST failed
Process "Check Syntax" did not complete.


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Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS2\FPGA_LMS/cosfunc.vhd. Ignore this file from project file lms_vhdl.prj.
Compiling vhdl file F:/FPGA_LMS2/FPGA_LMS/LMS.vhd in Library work.
ERROR:HDLParsers:3292 - F:/FPGA_LMS2/FPGA_LMS/LMS.vhd Line 90. + has two possible definitions in this scope.  For example, parameter 1 (result of operator) can be: std_logic_vector or SIGNED
ERROR:HDLParsers:1411 - F:/FPGA_LMS2/FPGA_LMS/LMS.vhd Line 95. Parameter waveOut of mode out can not be associated with a formal parameter of mode in.
ERROR: XST failed
Process "Check Syntax" did not complete.


Project Navigator Auto-Make Log File
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Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS2\FPGA_LMS/cosfunc.vhd. Ignore this file from project file lms_vhdl.prj.
Compiling vhdl file F:/FPGA_LMS2/FPGA_LMS/LMS.vhd in Library work.
ERROR:HDLParsers:3292 - F:/FPGA_LMS2/FPGA_LMS/LMS.vhd Line 90. + has two possible definitions in this scope.  For example, parameter 1 (result of operator) can be: std_logic_vector or SIGNED
ERROR: XST failed
Process "Check Syntax" did not complete.


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Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS2\FPGA_LMS/cosfunc.vhd. Ignore this file from project file lms_vhdl.prj.
Compiling vhdl file F:/FPGA_LMS2/FPGA_LMS/LMS.vhd in Library work.
Entity <lms> (Architecture <behav>) compiled.
Completed process "Check Syntax".



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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS2\FPGA_LMS/cosfunc.vhd. Ignore this file from project file lms_vhdl.prj.
Compiling vhdl file F:/FPGA_LMS2/FPGA_LMS/LMS.vhd in Library work.
Architecture behav of Entity lms is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <lms> (Architecture <behav>).
WARNING:Xst:766 - F:/FPGA_LMS2/FPGA_LMS/LMS.vhd line 67: Generating a Black Box for component <cosfunc>.
Entity <lms> analyzed. Unit <lms> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <lms>.
    Related source file is F:/FPGA_LMS2/FPGA_LMS/LMS.vhd.
    Found 8-bit register for signal <waveOut>.
    Found 16-bit adder for signal <$n0000> created at line 92.
    Found 8x8-bit multiplier for signal <$n0002> created at line 119.
    Found 8x8-bit multiplier for signal <$n0003> created at line 124.
    Found 8-bit subtractor for signal <$n0009> created at line 96.
    Found 8x8-bit multiplier for signal <$n0010> created at line 90.
    Found 8x8-bit multiplier for signal <$n0011> created at line 92.
    Found 1-bit register for signal <ACLR>.
    Found 1-bit register for signal <CE>.
    Found 8-bit register for signal <err>.
    Found 6-bit up counter for signal <sTHETA>.
    Found 8-bit up accumulator for signal <Wcos>.
    Found 8-bit up accumulator for signal <Wsin>.
    Summary:
	inferred   1 Counter(s).
	inferred   2 Accumulator(s).
	inferred  10 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   4 Multiplier(s).
Unit <lms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Multipliers                      : 4
 8x8-bit multiplier                : 4
# Adders/Subtractors               : 2
 8-bit subtractor                  : 1
 16-bit adder                      : 1
# Counters                         : 1
 6-bit up counter                  : 1
# Accumulators                     : 2
 8-bit up accumulator              : 2
# Registers                        : 4
 1-bit register                    : 2
 8-bit register                    : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: Executing edif2ngd -noa "cosfunc.edn" "cosfunc.ngo"
INFO:NgdBuild - Release 6.2.03i - edif2ngd G.31a
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "cosfunc.ngo"...
Loading core <cosfunc> for timing and area information for instance <U1>.

Optimizing unit <lms> ...
Loading device for application Xst from file '2v1000.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block lms, actual ratio is 0.
WARNING:Xst:382 - Register BU30 is equivalent to BU15
WARNING:Xst:382 - Register BU32 is equivalent to BU17
WARNING:Xst:382 - Register BU34 is equivalent to BU19
WARNING:Xst:382 - Register BU36 is equivalent to BU21
WARNING:Xst:382 - Register BU38 is equivalent to BU23
WARNING:Xst:382 - Register BU40 is equivalent to BU25
FlipFlop err_7 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v1000fg256-4 

 Number of Slices:                      50  out of   5120     0%  
 Number of Slice Flip Flops:            71  out of  10240     0%  
 Number of 4 input LUTs:                49  out of  10240     0%  
 Number of bonded IOBs:                 25  out of    172    14%  
 Number of BRAMs:                        1  out of     40     2%  
 Number of MULT18X18s:                   4  out of     40    10%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 72    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 12.706ns (Maximum Frequency: 78.706MHz)
   Minimum input arrival time before clock: 4.041ns
   Maximum output required time after clock: 5.838ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



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Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS2\FPGA_LMS/cosfunc.vhd. Ignore this file from project file lms_vhdl.prj.
Compiling vhdl file F:/FPGA_LMS2/FPGA_LMS/LMS.vhd in Library work.
Entity <lms> (Architecture <behav>) compiled.
Completed process "Check Syntax".



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Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS2\FPGA_LMS/cosfunc.vhd. Ignore this file from project file lms_vhdl.prj.
Compiling vhdl file F:/FPGA_LMS2/FPGA_LMS/LMS.vhd in Library work.
Architecture behav of Entity lms is up to date.
Completed process "Check Syntax".



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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS2\FPGA_LMS/cosfunc.vhd. Ignore this file from project file lms_vhdl.prj.
Compiling vhdl file F:/FPGA_LMS2/FPGA_LMS/LMS.vhd in Library work.
Architecture behav of Entity lms is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <lms> (Architecture <behav>).
WARNING:Xst:766 - F:/FPGA_LMS2/FPGA_LMS/LMS.vhd line 69: Generating a Black Box for component <cosfunc>.
Entity <lms> analyzed. Unit <lms> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <lms>.
    Related source file is F:/FPGA_LMS2/FPGA_LMS/LMS.vhd.
WARNING:Xst:1306 - Output <waveOut> is never assigned.
WARNING:Xst:646 - Signal <Qsin<15>> is assigned but never used.
WARNING:Xst:646 - Signal <Qsin<6:0>> is assigned but never used.
WARNING:Xst:646 - Signal <Qcos<15>> is assigned but never used.