__projnav.log

来自「VHDL写的LMS算法程序。利用本地正弦信号」· LOG 代码 · 共 1,677 行 · 第 1/5 页

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Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Adders/Subtractors               : 2 12-bit adder                      : 1 12-bit subtractor                 : 1# Counters                         : 1 6-bit up counter                  : 1# Registers                        : 3 1-bit register                    : 2 12-bit register                   : 1==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Launcher: "cosfunc.ngo" is up to date.Launcher: "multiplier.ngo" is up to date.Loading core <cosfunc> for timing and area information for instance <U1>.Loading core <multiplier> for timing and area information for instance <U2>.Loading core <multiplier> for timing and area information for instance <U3>.WARNING:Xst:1710 - FF/Latch  <err_10> (without init value) is constant in block <lms>.Optimizing unit <lms> ...Loading device for application Xst from file '2v1000.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block lms, actual ratio is 1.WARNING:Xst:382 - Register BU30 is equivalent to BU15WARNING:Xst:382 - Register BU32 is equivalent to BU17WARNING:Xst:382 - Register BU34 is equivalent to BU19WARNING:Xst:382 - Register BU36 is equivalent to BU21WARNING:Xst:382 - Register BU38 is equivalent to BU23WARNING:Xst:382 - Register BU40 is equivalent to BU25=========================================================================*                            Final Report                               *=========================================================================Device utilization summary:---------------------------Selected Device : 2v1000fg256-4  Number of Slices:                      94  out of   5120     1%   Number of Slice Flip Flops:           153  out of  10240     1%   Number of 4 input LUTs:                34  out of  10240     0%   Number of bonded IOBs:                 37  out of    172    21%   Number of BRAMs:                        1  out of     40     2%   Number of MULT18X18s:                   2  out of     40     5%   Number of GCLKs:                        1  out of     16     6%  =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+CLK                                | BUFGP                  | 156   |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -4   Minimum period: 7.796ns (Maximum Frequency: 128.263MHz)   Minimum input arrival time before clock: 4.253ns   Maximum output required time after clock: 9.830ns   Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".

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Started process "View VHDL Instantiation Template".WARNING:HDLParsers:3481 - No primary, secondary unit in the file   F:\FPGA_LMS/multiplier.vhd. Ignore this file from project file   pepExtractor.prj.WARNING:HDLParsers:3481 - No primary, secondary unit in the file   F:\FPGA_LMS/cosfunc.vhd. Ignore this file from project file pepExtractor.prj.Compiling vhdl file F:/FPGA_LMS/LMS.vhd in Library work.Entity <lms> (Architecture <behav>) compiled.tdtfi(vhdl) completed successfully.Completed process "View VHDL Instantiation Template".


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WARNING:HDLParsers:3481 - No primary, secondary unit in the file   F:\FPGA_LMS/multiplier.vhd. Ignore this file from project file   pepExtractor.prj.WARNING:HDLParsers:3481 - No primary, secondary unit in the file   F:\FPGA_LMS/cosfunc.vhd. Ignore this file from project file pepExtractor.prj.Compiling vhdl file F:/FPGA_LMS/LMS.vhd in Library work.Entity <lms> (Architecture <behav>) compiled.tdtfi(vhdl) completed successfully.


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WARNING:HDLParsers:3481 - No primary, secondary unit in the file   F:\FPGA_LMS2\FPGA_LMS/cosfunc_test.vhd. Ignore this file from project file   pepExtractor.prj.
Error creating test2.vhd. Defaulting to boilerplate test bench.


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WARNING:HDLParsers:3481 - No primary, secondary unit in the file   F:\FPGA_LMS2\FPGA_LMS/cosfunc_test.vhd. Ignore this file from project file   pepExtractor.prj.
Error creating test2.vhd. Defaulting to boilerplate test bench.


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