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Project Navigator Auto-Make Log File
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Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS/multiplier.vhd. Ignore this file from project file lms_vhdl.prj.
WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS/cosfunc.vhd. Ignore this file from project file lms_vhdl.prj.
Compiling vhdl file F:/FPGA_LMS/LMS.vhd in Library work.
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 65. Null range: 5 to 0
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 66. Null range: 11 to 0
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 67. Null range: 11 to 0
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 68. Null range: 11 to 0
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 70. Null range: 11 to 0
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 71. Null range: 11 to 0
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 84. Index size for dimension 1 of sTHETA is not 6.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 88. Index size for dimension 1 of SinOut is not 12.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 89. Index size for dimension 1 of CosOut is not 12.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 95. Index size for dimension 1 of SinOut is not 12.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 96. Index size for dimension 1 of err is not 12.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 97. Index size for dimension 1 of sOut is not 12.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 105. Index size for dimension 1 of CosOut is not 12.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 106. Index size for dimension 1 of err is not 12.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 107. Index size for dimension 1 of cOut is not 12.
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 114. Null range: 11 to 0
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 124. Null range: 9 to 0
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 124. Null range: 10 to 1
ERROR:HDLParsers:3367 - F:/FPGA_LMS/LMS.vhd Line 126. 10 is not included in the index range, 11 to 0, of array temp.
ERROR:HDLParsers:3384 - F:/FPGA_LMS/LMS.vhd Line 161. String Literal "000000" is not of size 0.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 169. Index size for dimension 1 of err is not 12.
ERROR: XST failed
Process "Check Syntax" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS/multiplier.vhd. Ignore this file from project file lms_vhdl.prj.
WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS/cosfunc.vhd. Ignore this file from project file lms_vhdl.prj.
Compiling vhdl file F:/FPGA_LMS/LMS.vhd in Library work.
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 65. Null range: 5 to 0
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 66. Null range: 11 to 0
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 67. Null range: 11 to 0
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 68. Null range: 11 to 0
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 70. Null range: 11 to 0
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 71. Null range: 11 to 0
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 84. Index size for dimension 1 of sTHETA is not 6.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 88. Index size for dimension 1 of SinOut is not 12.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 89. Index size for dimension 1 of CosOut is not 12.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 95. Index size for dimension 1 of SinOut is not 12.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 96. Index size for dimension 1 of err is not 12.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 97. Index size for dimension 1 of sOut is not 12.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 105. Index size for dimension 1 of CosOut is not 12.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 106. Index size for dimension 1 of err is not 12.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 107. Index size for dimension 1 of cOut is not 12.
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 114. Null range: 11 to 0
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 124. Null range: 10 to 1
ERROR:HDLParsers:3367 - F:/FPGA_LMS/LMS.vhd Line 124. 11 is not included in the index range, 11 to 0, of array temp.
ERROR:HDLParsers:3384 - F:/FPGA_LMS/LMS.vhd Line 161. String Literal "000000" is not of size 0.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 169. Index size for dimension 1 of err is not 12.
ERROR: XST failed
Process "Check Syntax" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS/multiplier.vhd. Ignore this file from project file lms_vhdl.prj.
WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS/cosfunc.vhd. Ignore this file from project file lms_vhdl.prj.
Compiling vhdl file F:/FPGA_LMS/LMS.vhd in Library work.
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 65. Null range: 5 to 0
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 66. Null range: 11 to 0
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 67. Null range: 11 to 0
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 68. Null range: 11 to 0
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 70. Null range: 11 to 0
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 71. Null range: 11 to 0
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 84. Index size for dimension 1 of sTHETA is not 6.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 88. Index size for dimension 1 of SinOut is not 12.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 89. Index size for dimension 1 of CosOut is not 12.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 95. Index size for dimension 1 of SinOut is not 12.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 96. Index size for dimension 1 of err is not 12.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 97. Index size for dimension 1 of sOut is not 12.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 105. Index size for dimension 1 of CosOut is not 12.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 106. Index size for dimension 1 of err is not 12.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 107. Index size for dimension 1 of cOut is not 12.
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 114. Null range: 11 to 0
WARNING:HDLParsers:3335 - F:/FPGA_LMS/LMS.vhd Line 124. Null range: 10 to 1
ERROR:HDLParsers:3367 - F:/FPGA_LMS/LMS.vhd Line 124. 11 is not included in the index range, 11 to 0, of array temp.
ERROR:HDLParsers:3384 - F:/FPGA_LMS/LMS.vhd Line 161. String Literal "000000" is not of size 0.
ERROR:HDLParsers:837 - F:/FPGA_LMS/LMS.vhd Line 169. Index size for dimension 1 of err is not 12.
ERROR: XST failed
Process "Check Syntax" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS/multiplier.vhd. Ignore this file from project file lms_vhdl.prj.
WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS/cosfunc.vhd. Ignore this file from project file lms_vhdl.prj.
Compiling vhdl file F:/FPGA_LMS/LMS.vhd in Library work.
Entity <LMS> (Architecture <Behav>) compiled.
Completed process "Check Syntax".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS/multiplier.vhd. Ignore this file from project file lms_vhdl.prj.
WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS/cosfunc.vhd. Ignore this file from project file lms_vhdl.prj.
Compiling vhdl file F:/FPGA_LMS/LMS.vhd in Library work.
Architecture behav of Entity lms is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <lms> (Architecture <behav>).
WARNING:Xst:766 - F:/FPGA_LMS/LMS.vhd line 82: Generating a Black Box for component <cosfunc>.
WARNING:Xst:766 - F:/FPGA_LMS/LMS.vhd line 92: Generating a Black Box for component <multiplier>.
WARNING:Xst:766 - F:/FPGA_LMS/LMS.vhd line 102: Generating a Black Box for component <multiplier>.
Entity <lms> analyzed. Unit <lms> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <lms>.
    Related source file is F:/FPGA_LMS/LMS.vhd.
    Register <sclear> equivalent to <sACLR> has been removed
    Found 12-bit subtractor for signal <$n0000> created at line 122.
    Found 12-bit adder for signal <$n0004> created at line 171.
    Found 1-bit register for signal <ClkEN>.
    Found 12-bit register for signal <err>.
    Found 1-bit register for signal <sACLR>.
    Found 6-bit up counter for signal <sTHETA>.
    Summary:
	inferred   1 Counter(s).
	inferred  14 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
Unit <lms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 2
 12-bit adder                      : 1
 12-bit subtractor                 : 1
# Counters                         : 1
 6-bit up counter                  : 1
# Registers                        : 3
 1-bit register                    : 2
 12-bit register                   : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: Executing edif2ngd -noa "cosfunc.edn" "cosfunc.ngo"
INFO:NgdBuild - Release 6.2.03i - edif2ngd G.31a
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "cosfunc.ngo"...
Launcher: Executing edif2ngd -noa "multiplier.edn" "multiplier.ngo"
INFO:NgdBuild - Release 6.2.03i - edif2ngd G.31a
INFO:NgdBuild - Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Writing the design to "multiplier.ngo"...
Loading core <cosfunc> for timing and area information for instance <U1>.
Loading core <multiplier> for timing and area information for instance <U2>.
Loading core <multiplier> for timing and area information for instance <U3>.
WARNING:Xst:1710 - FF/Latch  <err_10> (without init value) is constant in block <lms>.

Optimizing unit <lms> ...
Loading device for application Xst from file '2v1000.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block lms, actual ratio is 1.
WARNING:Xst:382 - Register BU30 is equivalent to BU15
WARNING:Xst:382 - Register BU32 is equivalent to BU17
WARNING:Xst:382 - Register BU34 is equivalent to BU19
WARNING:Xst:382 - Register BU36 is equivalent to BU21
WARNING:Xst:382 - Register BU38 is equivalent to BU23
WARNING:Xst:382 - Register BU40 is equivalent to BU25

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v1000fg256-4 

 Number of Slices:                      94  out of   5120     1%  
 Number of Slice Flip Flops:           153  out of  10240     1%  
 Number of 4 input LUTs:                34  out of  10240     0%  
 Number of bonded IOBs:                 37  out of    172    21%  
 Number of BRAMs:                        1  out of     40     2%  
 Number of MULT18X18s:                   2  out of     40     5%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 156   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 7.796ns (Maximum Frequency: 128.263MHz)
   Minimum input arrival time before clock: 4.253ns
   Maximum output required time after clock: 9.830ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS/multiplier.vhd. Ignore this file from project file lms_vhdl.prj.
WARNING:HDLParsers:3481 - No primary, secondary unit in the file F:\FPGA_LMS/cosfunc.vhd. Ignore this file from project file lms_vhdl.prj.
Compiling vhdl file F:/FPGA_LMS/LMS.vhd in Library work.
Entity <lms> (Architecture <behav>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <lms> (Architecture <behav>).
WARNING:Xst:766 - F:/FPGA_LMS/LMS.vhd line 82: Generating a Black Box for component <cosfunc>.
WARNING:Xst:766 - F:/FPGA_LMS/LMS.vhd line 92: Generating a Black Box for component <multiplier>.
WARNING:Xst:766 - F:/FPGA_LMS/LMS.vhd line 102: Generating a Black Box for component <multiplier>.
Entity <lms> analyzed. Unit <lms> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <lms>.
    Related source file is F:/FPGA_LMS/LMS.vhd.
    Register <sclear> equivalent to <sACLR> has been removed
    Found 12-bit subtractor for signal <$n0000> created at line 122.
    Found 12-bit adder for signal <$n0004> created at line 171.
    Found 1-bit register for signal <ClkEN>.
    Found 12-bit register for signal <err>.
    Found 1-bit register for signal <sACLR>.
    Found 6-bit up counter for signal <sTHETA>.
    Summary:
	inferred   1 Counter(s).
	inferred  14 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
Unit <lms> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================