📄 lms.gfl

📁 VHDL写的LMS算法程序。利用本地正弦信号
💻 GFL
📖 第 1 页 / 共 2 页
字号:
12 下一页
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
# xst flow : RunXST
lms.syr
lms.prj
lms.sprj
lms.ana
lms.stx
lms.cmd_log
lms.ngc
lms.ngr
# View RTL Schematic
lms.ngr
# ModelSim : Launch ModelSim Simulator
lms.ldo
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# XST (Creating Lso File) : 
lms.lso
# xst flow : RunXST
lms.syr
lms.prj
lms.sprj
lms.ana
lms.stx
lms.cmd_log
lms.ngc
lms.ngr
# VHDL : View VHDL Instantiation Template
__projnav/tb.rsp
lms.vhi
__projnav/vhd2vhi.err
# ModelSim : Launch ModelSim Simulator
lms.ldo
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Launch ModelSim Simulator
vsim.wlf
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.rsp
coregen.prj
coregen.fin
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# ModelSim : Simulate Behavioral VHDL Model
testbench.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
testbench.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
testbench.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# ModelSim : Simulate Behavioral VHDL Model
test_test_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) : 
lms.lso
# xst flow : RunXST
lms.syr
lms.prj
lms.sprj
lms.ana
lms.stx
lms.cmd_log
lms.ngc
lms.ngr
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) : 
lms.lso
# xst flow : RunXST
lms.syr
lms.prj
lms.sprj
lms.ana
lms.stx
lms.cmd_log
lms.ngc
lms.ngr
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) : 
lms.lso
# xst flow : RunXST
lms.syr
lms.prj
lms.sprj
lms.ana
lms.stx
lms.cmd_log
lms.ngc
lms.ngr
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ProjNav -> New -> Test Bench
__projnav/createTB.err
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_fortest_vhd_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) : 
lms.lso
# xst flow : RunXST
lms.syr
lms.prj
lms.sprj
lms.ana
lms.stx
lms.cmd_log
lms.ngc
lms.ngr
# XST (Creating Lso File) : 
lms.lso
# xst flow : RunXST
lms.syr
lms.prj
lms.sprj
lms.ana
lms.stx
lms.cmd_log
lms.ngc
lms.ngr
# Editing Cores
__projnav/_createCoregen.rsp
__projnav/launchCoregen.rsp
# ModelSim : Simulate Behavioral VHDL Model
lms_test_tb.fdo
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# ModelSim : Simulate Behavioral VHDL Model
vsim.wlf
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) : 
lms.lso
# Check Syntax
lms.stx
lms.ngc
# XST (Creating Lso File) : 
lms.lso
# xst flow : RunXST
lms.syr
lms.prj
lms.sprj
lms.ana
lms.stx
lms.cmd_log
lms.ngc
lms.ngr
12 下一页
💿 文件大小 265 K
👤 上传用户 weizik
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#VHDL #LMS #算法 #程序
⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -