ad.vhd

来自「输入为8421BCD码」· VHDL 代码 · 共 52 行

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_UNSIGNED.ALL;


ENTITY   AD IS 
     PORT( A  : IN  STD_LOGIC_VECTOR (3 DOWNTO 0);
           B  : IN  STD_LOGIC_VECTOR (3 DOWNTO 0);
           SS : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)

          );
     END  AD;
ARCHITECTURE  ADDPING OF  AD IS
       
         
    
         BEGIN
                            
         p1: PROCESS (A,B)
         VARIABLE  TEM1,TEM2:STD_LOGIC_VECTOR (3 DOWNTO 0);
         VARIABLE  TEM3,TEM4:STD_LOGIC_VECTOR (4 DOWNTO 0);
          VARIABLE  TEM:STD_LOGIC;



             BEGIN
             TEM1:= A + 3;
             TEM2:= B+3;
             TEM3:=TEM1+TEM2;
           IF (TEM3(4)='1') THEN
             TEM3:=TEM3+3;
             ELSE  
              TEM3:=TEM3-3;    
                
           
           END IF;
              TEM4:=TEM3-3;
              SS<=TEM4;
          END PROCESS P1;


       END  ADDPING;