user_app.vhd

VHDL编写的PCI代码,PCI2.2兼容,Xillinx Virtex与Spantan II 优化,33M主频,32位宽度,全目标功能等.

--*****************************************************************************
--*                                                                           *
--*            EuCore PCI-T32 - PCI Target Interface Core                     *
--*            (C)2000 MaxLock, Inc. All rights reserved                      *
--*                                                                           *
--*****************************************************************************
-- DESIGN  : PCI-T32 Example Application 1
-- FILE    : USER_APP.vhd
-- DATE    : 10.1.2001
-- REVISION: 1.1
-- DESIGNER: Tony
-- Descr   : User Application - Simple ALU
-- Entities: USER_APP
-- Changes :                                                    
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all; 
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity USER_APP is
   port (
      APP_RST : in std_logic;
      APP_CLK : in std_logic;
      APP_ADR : in std_logic_vector(31 downto 0);
      APP_ADI : in std_logic_vector(31 downto 0);
      APP_ADO : out std_logic_vector(31 downto 0);
      APP_INTn : out std_logic;
      T_DRDY : out std_logic;
      T_ABORT : out std_logic;
      T_TERM : out std_logic;
      T_BARHIT : in std_logic_vector(5 downto 0);
      T_EBARHIT : in std_logic;
      T_BEn : in std_logic_vector(3 downto 0);
      T_CMD : in std_logic_vector(3 downto 0);
      T_RD : in std_logic;
      T_WR : in std_logic;
      T_WE : in std_logic;
      T_NEXTD : in std_logic;
      PCR_CMD : in std_logic_vector(15 downto 0); 
      PCR_STAT : in std_logic_vector(15 downto 0)
      ----------------------------
      -- Add user I/O pins here --
      ----------------------------
   );
end USER_APP;      

architecture Struct of USER_APP is 
   -- Component declaration of the USER_ALU unit
   -- File name contains USER_ALU entity: .\USER_ALU.vhd
   component USER_ALU
   port(
      RESET : in std_logic;
      CLK : in std_logic;
      ADR : in std_logic_vector(31 downto 0);
      ADi : in std_logic_vector(31 downto 0);
      ADo : out std_logic_vector(31 downto 0);
      HIT : in std_logic;
      BEn : in std_logic_vector(3 downto 0);
      RD : in std_logic;
      WR : in std_logic;
      WE : in std_logic;
      NEXTD : in std_logic;
      DRDY : out std_logic
      );
   end component;

   signal ALU_DRDY : std_logic;

begin
   -- T_DRDY assignment
   T_DRDY <= ALU_DRDY;
   --
   --
   T_ABORT <= '0';
   T_TERM <= '0';
   APP_INTn <='1';
   -- USER_ALU component instantiation
   U1: USER_ALU port map(
      RESET => APP_RST,
      CLK   => APP_CLK,
      ADR   => APP_ADR,
      ADi   => APP_ADi,
      ADo   => APP_ADo,
      HIT   => T_BARHIT(0),
      BEn   => T_BEn,
      RD    => T_RD,
      WR    => T_WR,
      WE    => T_WE,
      NEXTD => T_NEXTD,
      DRDY  => ALU_DRDY
      );
end Struct;