cfg_regs.vhd

VHDL编写的PCI代码,PCI2.2兼容,Xillinx Virtex与Spantan II 优化,33M主频,32位宽度,全目标功能等.

--*****************************************************************************
--*                                                                           *
--*            EuCore PCI-T32 - PCI Target Interface Core                     *
--*            (C)2000 MaxLock, Inc. All rights reserved                      *
--*                                                                           *
--*****************************************************************************
-- FILE    : PCI_CFGREG
-- DATE    : 10.1.2001
-- REVISION: 1.1
-- DESIGNER: Tony
-- Descr   : PCI Configuration Space Registers for Target-only Interface
-- Entities:   
--             CFG_STREG
--             CFG_CMDREG
--             BAR_REG
--             EBAR
--             CFG_INTREG
-- Changes :
--           5.1.2001 - CFG_STREG - added PCR_STAT port for register contens 
--                      visibility
--                    - CFG_CMDREG - added PCR_CMD port for register contens 
--                      visibility                
--
--*****************************************************************************
--*               Command Register                                            *
--*****************************************************************************
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.CFGSPACE_SET.all;
entity CFG_CMDREG is
  port(
      RESET       : in  std_logic;
      CLK         : in  std_logic;
      DIN         : in  std_logic_vector(15 downto 0);-- Data IN
      DOUT        : out std_logic_vector(15 downto 0);-- Data OUT
      BEn         : in  std_logic_vector(3 downto 0); -- Byte Enables
      WE          : in  std_logic;
      OE          : in  std_logic;
      PCR_CMD     : out std_logic_vector(15 downto 0); -- PCI Cfg. Command reg.
      IO_EN       : out std_logic;     -- I/O Space Decoding Enabled
      MEM_EN      : out std_logic;     -- Memory Space Decoding Enabled
      SPEC_CYC    : out std_logic;     -- Special Cycles Monitoring Enabled
      PERR_EN     : out std_logic;     -- Parity Error Response
      STEPPING_EN : out std_logic;     -- Stepping Control
      SERR_EN     : out std_logic      -- SERR# Enable
  ); 
end CFG_CMDREG;
--
-- Command Register RTL Architecture 
--
architecture RTL of CFG_CMDREG is
  signal Settings : std_logic_vector(15 downto 0);
begin
    -- Register
   INTREG: process (CLK, RESET)
   begin
      if RESET='1' then	--asynchronous RESET active High
         Settings <= COMMAND_INIT;
      elsif (CLK'event and CLK='1') then  --CLK rising edge
         if WE = '1' then
            if BEn(0)='0' then
               Settings(1 downto 0) <= DIN(1 downto 0);
               Settings(2) <= '0';       -- Master not supported
               Settings(3) <= DIN(3);
               Settings(4) <= '0';       -- MWI not supported
               Settings(5) <= '0';             
               Settings(6) <= DIN(6);             
               Settings(7) <= '0';             
--               Settings(7) <= DIN(7);  -- Stepping not supported
            end if;
            if BEn(1)='0' then   
               Settings(15 downto 10) <= "000000";
               Settings(9 downto 8) <= DIN(9 downto 8);
            end if;
         end if;
      end if;
   end process;
   -- Output Tristate Buffer
   O_BUF: DOUT <= Settings when OE='1' else "ZZZZZZZZZZZZZZZZ";
   PCR_CMD  <= Settings;    -- Command Register bits assignment   
   IO_EN    <= Settings(0);   -- I/O Space Decoding Enabled
   MEM_EN   <= Settings(1);   -- Memory Space Decoding Enabled
   SPEC_CYC <= Settings(3);   -- Special Cycles Monitoring Enabled
   PERR_EN  <= Settings(6);   -- Parity Error Response
   STEPPING_EN <= Settings(7);-- Stepping Control
   SERR_EN     <= Settings(8);-- SERR# Enable
end RTL; -- CFG_CMDREG
--
--*****************************************************************************
--*                    Status Register                                        *
--*****************************************************************************
--
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.CFGSPACE_SET.all;
entity CFG_STREG is
  port(
      RESET     : in  std_logic;
      CLK       : in  std_logic;
      DIN       : in  std_logic_vector(15 downto 0);-- Data IN
      DOUT      : out std_logic_vector(15 downto 0);-- Data OUT
      BEn       : in  std_logic_vector(3 downto 0);
      WE        : in  std_logic;
      OE        : in  std_logic;
      SET_MDPERR: in  std_logic; -- Set Master Data Parity Error Bit( 8)
      SIG_TABORT: in  std_logic; -- Set Signaled Target Abort Bit   (11)
      RCV_TABORT: in  std_logic; -- Set Received Target Abort Bit   (12)
      RCV_MABORT: in  std_logic; -- Set Received Master Abort Bit   (13)
      SIG_SERR  : in  std_logic; -- Set Signaled System Error Bit   (14)
      DET_PERR  : in  std_logic;  -- Set Detected Parity Error Bit   (15)
      PCR_STAT  : out std_logic_vector(15 downto 0) -- PCI Cfg. Status Register Contens 
  ); end CFG_STREG;
--
-- Status Register RTL Architecture 
--
architecture RTL of CFG_STREG is
  signal Status : std_logic_vector(15 downto 0);
begin                                
   Status(7 downto 0) <= STATUS_INIT(7 downto 0);
   Status(10 downto 9) <= STATUS_INIT(10 downto 9);
   --
   CSRREG: process (CLK, RESET)
   begin
      if RESET='1' then	--asynchronous RESET active High
         Status(15) <= STATUS_INIT(15);
         Status(14) <= STATUS_INIT(14);
         Status(13) <= STATUS_INIT(13);
         Status(12) <= STATUS_INIT(12);
         Status(11) <= STATUS_INIT(11);
         Status(8) <= STATUS_INIT(8);
      elsif (CLK'event and CLK='1') then  --CLK rising edge
         if (WE = '1') and (BEn(3)='0')then
            -- RESET of Status Bits
            if DIN(15)='1' then
               Status(15) <='0';
            end if;
            if DIN(14)='1' then
               Status(14) <='0';
            end if;
            if DIN(13)='1' then
               Status(13) <='0';
            end if;
            if DIN(12)='1' then
               Status(12) <='0';
            end if;
            if DIN(11)='1' then
               Status(11) <='0';
            end if;
            if DIN(8)='1' then
               Status(8) <='0';
            end if;  
         else
            if DET_PERR = '1' then
               Status(15) <='1';
            end if;
            if SIG_SERR = '1' then
               Status(14) <='1';
            end if;
            if RCV_MABORT = '1' then
               Status(13) <='1';
            end if;
            if RCV_TABORT = '1' then
               Status(12) <='1';
            end if;
            if  SIG_TABORT = '1' then
               Status(11) <='1';
            end if;
            if SET_MDPERR = '1' then
               Status(8) <='1';
            end if;
         end if;
      end if;
   end process;
   -- Output Tristate Buffer
   O_BUF: DOUT <= Status when OE='1' else "ZZZZZZZZZZZZZZZZ";                   
   PCR_STAT <= Status;   
end RTL; -- CFG_STREG 

--
--*****************************************************************************
--*                    Generic Base Address Register                          *
--*****************************************************************************
--
library IEEE;
use IEEE.std_logic_1164.all;
library WORK;
use WORK.CFGSPACE_SET.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity BAR_REG is
   generic(
      BAR_NO: integer:= 0);
   port(
      RESET       : in  std_logic;