core_set.vhd

VHDL编写的PCI代码,PCI2.2兼容,Xillinx Virtex与Spantan II 优化,33M主频,32位宽度,全目标功能等.

--*****************************************************************************
--*                                                                           *
--*            EuCore PCI-T32 - PCI Target Interface Core                     *
--*            (C)2000 MaxLock, Inc. All rights reserved                      *
--*                                                                           *
--*****************************************************************************
-- FILE    : CORE_SET.VHD
-- DATE    : 10.1.2001
-- REVISION: 1.1
-- DESIGNER: Tony
-- Descr   : PCI Core Parameters
-- Entities: package CFGSPACE_SET - register and system settings
--           package PCI_COMMANDS - command binary codes
-- Changes :
--
--
-------------------------------------------------------------------------------
--
-- ********************************************************
-- *          Configuration Space Parameters              *
-- ********************************************************
library IEEE;
use IEEE.std_logic_1164.all;
package CFGSPACE_SET is 
   -- Vendor ID                                         FEDCBA9876543210
   constant VENDOR_ID : std_logic_vector(15 downto 0):="1010101111001101"; -- Vendor ID = xABCD (void)
   -- Device ID                                         FEDCBA9876543210
   constant DEVICE_ID : std_logic_vector(15 downto 0):="0000000100000000"; -- Device ID = x0100 
   --  Class ID & SubClass & Interface                76543210     76543210     76543210
   constant CLASS_ID: std_logic_vector(23 downto 0):="00010000" & "00000000" & "00000000";
   -- Revision ID                                  76543210
   constant REV_ID: std_logic_vector(7 downto 0):="00010000"; -- Revision ID = 1.0
   ------------------------------------
   --         BAR0 Settings          --
   ------------------------------------
   constant BAR0_PRESENT: boolean:= TRUE;
   -- Base Address Register 0                         33222222222211111111110000000000
   -- Mapping Infrmation                              10987654321098765432109876543210
   constant BAR0_MAP: std_logic_vector(31 downto 0):="11111111111111111111111111110000";
   constant BAR0_DWIDTH: integer := 28; -- number of decoded address bist (1's from left in BAR0_SET)
   ------------------------------------
   --         BAR1 Settings          --
   ------------------------------------
   constant BAR1_PRESENT: boolean:= FALSE;
   -- Base Address Register 1                         33222222222211111111110000000000
   -- Mapping Infrmation                              10987654321098765432109876543210
   constant BAR1_MAP: std_logic_vector(31 downto 0):="00000000000000000000000000000000";
   constant BAR1_DWIDTH: integer := 28;
   ------------------------------------
   --         BAR2 Settings          --
   ------------------------------------
   constant BAR2_PRESENT: boolean:= FALSE;
   -- Base Address Register 2                         33222222222211111111110000000000
   -- Mapping Infrmation                              10987654321098765432109876543210
   constant BAR2_MAP: std_logic_vector(31 downto 0):="00000000000000000000000000000000";
   constant BAR2_DWIDTH: integer := 28;
   ------------------------------------
   --         BAR3 Settings          --
   ------------------------------------
   constant BAR3_PRESENT: boolean:= FALSE;
   -- Base Address Register 3                         33222222222211111111110000000000
   -- Mapping Infrmation                              10987654321098765432109876543210
   constant BAR3_MAP: std_logic_vector(31 downto 0):="00000000000000000000000000000000";
   constant BAR3_DWIDTH: integer := 28;
   ------------------------------------
   --         BAR4 Settings          --
   ------------------------------------
   constant BAR4_PRESENT: boolean:= FALSE;
   -- Base Address Register 4                         33222222222211111111110000000000
   -- Mapping Infrmation                              10987654321098765432109876543210
   constant BAR4_MAP: std_logic_vector(31 downto 0):="00000000000000000000000000000000";
   constant BAR4_DWIDTH: integer := 28;
   ------------------------------------
   --         BAR5 Settings          --
   ------------------------------------
   constant BAR5_PRESENT: boolean:= FALSE;
   -- Base Address Register 5                         33222222222211111111110000000000
   -- Mapping Infrmation                              10987654321098765432109876543210
   constant BAR5_MAP: std_logic_vector(31 downto 0):="00000000000000000000000000000000";
   constant BAR5_DWIDTH: integer := 28;
   ------------------------------------
   --  Expansion ROM BAR Settings    --
   ------------------------------------                               
   -- Expansion ROM must allocate space in interval 2kB upto 16MB
   constant EBAR_PRESENT: boolean:= FALSE;
   -- Expansion ROM Base Address Register             33222222222211111111110000000000
   -- Mapping Infrmation                              10987654321098765432109876543210
   constant EBAR_MAP: std_logic_vector(31 downto 0):="00000000000000000000000000000000";
   constant EBAR_DWIDTH: integer := 17;  --  
   --
   -- Subsystem Vendor ID                                  FEDCBA9876543210
   constant SUBVENDOR_ID : std_logic_vector(15 downto 0):="0001000011101110"; -- Vendor ID = x10EE (Xilinx)
   -- Subsystem Device ID                                  FEDCBA9876543210
   constant SUBDEVICE_ID : std_logic_vector(15 downto 0):="0000000100000000"; -- Device ID = x0100(Xilinx) 
   -- Capabilities Pointer                          76543210
   constant CAP_PTR: std_logic_vector(7 downto 0):="00000000"; --  
   -- Maximum Latency                               76543210
   constant MAX_LAT: std_logic_vector(7 downto 0):="00100000"; -- 
   -- Minimum Grant                                 76543210
   constant MIN_GNT: std_logic_vector(7 downto 0):="00000100"; -- 
   -- Interrupt Pin                                 76543210
   constant INT_PIN: std_logic_vector(7 downto 0):="00000001"; --  allowed values x00 = no interrup, x01= INTA#
   -- Interrupt Line                                 76543210
   constant INT_LINE: std_logic_vector(7 downto 0):="00000000"; --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
   -- Command Register Default Value              bit no.: FEDCBA9876543210 
   constant COMMAND_INIT :std_logic_vector(15 downto 0):= "0000000000000000"; 
   -- Status Register Default Value              bit no.: FEDCBA9876543210 
   constant STATUS_INIT :std_logic_vector(15 downto 0):= "0000001000000000"; 
   -- Cache Line Size Register Default Value
   constant CLSIZE_INIT :std_logic_vector(7 downto 0) := "00000000"; 
   -- Latency Timer Register Default Value
   constant LATTIMER_INIT :std_logic_vector(7 downto 0) := "00000000"; 
   -- Interrupt Line Register Default Value
   constant INTLINE_INIT :std_logic_vector(7 downto 0) := "00000000"; 
   constant BAR0_RO : std_logic_vector(3 downto 0):= BAR0_MAP(3 downto 0);-- BAR0 Lowest Nibble Value (Hard wired to this value)		
   constant BAR1_RO : std_logic_vector(3 downto 0):= BAR1_MAP(3 downto 0);-- BAR1 Lowest Nibble Value (Hard wired to this value)		
   constant BAR2_RO : std_logic_vector(3 downto 0):= BAR2_MAP(3 downto 0);-- BAR2 Lowest Nibble Value (Hard wired to this value)		
   constant BAR3_RO : std_logic_vector(3 downto 0):= BAR3_MAP(3 downto 0);-- BAR3 Lowest Nibble Value (Hard wired to this value)		
   constant BAR4_RO : std_logic_vector(3 downto 0):= BAR4_MAP(3 downto 0);-- BAR4 Lowest Nibble Value (Hard wired to this value)		
   constant BAR5_RO : std_logic_vector(3 downto 0):= BAR5_MAP(3 downto 0);-- BAR5 Lowest Nibble Value (Hard wired to this value)		
   -- Remap Address for reading addresses higher than 0x3F in CFG Space
   constant ROMADR_REMAP:std_logic_vector(3 downto 0) :="1110"; -- to reserved value at 0x38
   type BAR_RECORD is record
      PRESENT:BOOLEAN;
      BARMAP: std_logic_vector(31 downto 0);
      DWIDTH: integer;
   end record;
   type BAR_ARRAY is array (0 to 5) of BAR_RECORD;
   constant BAR_SET : BAR_ARRAY:= (
               BAR_RECORD'( BAR0_PRESENT,BAR0_MAP,BAR0_DWIDTH),
               BAR_RECORD'( BAR1_PRESENT,BAR1_MAP,BAR1_DWIDTH),
               BAR_RECORD'( BAR2_PRESENT,BAR2_MAP,BAR2_DWIDTH),
               BAR_RECORD'( BAR3_PRESENT,BAR3_MAP,BAR3_DWIDTH),
               BAR_RECORD'( BAR4_PRESENT,BAR4_MAP,BAR4_DWIDTH),
               BAR_RECORD'( BAR5_PRESENT,BAR5_MAP,BAR5_DWIDTH));
end CFGSPACE_SET;

library IEEE;
use IEEE.std_logic_1164.all;
package PCI_COMMANDS is
   constant IACK_CODE   :std_logic_vector(3 downto 0):="0000" ; -- Interrupt Acknowledge
   constant SCYC_CODE   :std_logic_vector(3 downto 0):="0001" ; -- Special Cycle
   constant IORD_CODE   :std_logic_vector(3 downto 0):="0010" ; -- I/O Read
   constant IOWR_CODE   :std_logic_vector(3 downto 0):="0011" ; -- I/O Write
   constant RES4_CODE   :std_logic_vector(3 downto 0):="0100" ; -- Reserved
   constant RES5_CODE   :std_logic_vector(3 downto 0):="0101" ; -- Reserved
   constant MRD_CODE    :std_logic_vector(3 downto 0):="0110" ; -- Memory Read
   constant MWR_CODE    :std_logic_vector(3 downto 0):="0111" ; -- Memory Write
   constant RES8_CODE   :std_logic_vector(3 downto 0):="1000" ; -- Reserved
   constant RES9_CODE   :std_logic_vector(3 downto 0):="1001" ; -- Reserved
   constant CFGRD_CODE  :std_logic_vector(3 downto 0):="1010" ; -- Configuration Read
   constant CFGWR_CODE  :std_logic_vector(3 downto 0):="1011" ; -- Configuration Write
   constant MRM_CODE    :std_logic_vector(3 downto 0):="1100" ; -- Memory Read Multiple
   constant DUAL_CODE   :std_logic_vector(3 downto 0):="1101" ; -- Dual Address Cycle
   constant MRL_CODE    :std_logic_vector(3 downto 0):="1110" ; -- Memory Read Line
   constant MWI_CODE    :std_logic_vector(3 downto 0):="1111" ; -- Memory Write and Invalidate
end PCI_COMMANDS;